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dc.contributor.authorKim, Kwanghyunen_US
dc.date.accessioned2014-08-13T14:40:09Z
dc.date.available2014-08-13T14:40:09Z
dc.date.issued1985en_US
dc.identifier.urihttp://hdl.handle.net/10919/50034
dc.format.extentxi, 144 leavesen_US
dc.format.mimetypeapplication/pdfen_US
dc.publisherVirginia Polytechnic Institute and State Universityen_US
dc.rightsThis Item is protected by copyright and/or related rights. Some uses of this Item may be deemed fair and permitted by law even without permission from the rights holder(s), or the rights holder(s) may have licensed the work for use under certain conditions. For other uses you need to obtain permission from the rights holder(s).en_US
dc.subject.lccLD5655.V855 1985.K538en_US
dc.subject.lcshIntegrated circuits -- Very large scale integrationen_US
dc.subject.lcshIntegrated circuits -- Design and construction -- Data processingen_US
dc.titleAn interactive design rule checker for integrated circuit layouten_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.description.degreeMaster of Scienceen_US
dc.identifier.oclc13017794en_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical Engineeringen_US
dc.type.dcmitypeTexten_US
dc.description.adminincomplete_metadataen_US


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