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dc.contributor.authorLee, Kevinen
dc.date.accessioned2015-06-26T08:00:29Zen
dc.date.available2015-06-26T08:00:29Zen
dc.date.issued2015-06-25en
dc.identifier.othervt_gsexam:5918en
dc.identifier.urihttp://hdl.handle.net/10919/53705en
dc.description.abstractThe modular design methodology has been widely adopted to harness the complexity of large FPGA-based systems. As a result, a number of commercial and academic tool flows emerged to support modular design including Hierarchical Design Flow and Partial Reconfiguration Flow, OpenPR, HMFlow, PARBIT, REPLICA, GoAhead and QFlow frameworks. As all of these projects have shown, a modular approach raises the abstraction level, provides clear boundaries for incremental design, reduces placement complexity, and improves productivity. At the physical layer, modules can be compiled into rectangular regions, suitable for placement on the FPGA fabric. Creating a design then becomes the process of placing all of the modules on the FPGA, followed by inter-module routing. FPGAs, however, are not homogenous, and the shape of individual modules could greatly impact overall device utilization. Prior work in modular assembly utilize modules with a single shape and aspect ratio in the assembly process. Due to the increasing size and heterogeneity of contemporary FPGAs, the placement flexibility of such a module is becoming increasingly limited. This thesis introduces a process that exploits offline shape generation and exploration, enabling the selection of shapes using criterias such as resource usage efficiency, placement flexibility, and device utilization. Module shapes can be generated with these criterias in mind while still taking advantage of the reduced placement complexity of modular design and assemblyen
dc.format.mediumETDen
dc.publisherVirginia Techen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectFPGAen
dc.subjectProductivityen
dc.subjectRapid Compilationen
dc.subjectModular Workflowen
dc.titleModule Shaping and Exploration in Rapid FPGA Design and Assembly Workflowsen
dc.typeThesisen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.description.degreeMaster of Scienceen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelmastersen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.disciplineComputer Engineeringen
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberPlassmann, Paul E.en
dc.contributor.committeememberMcGwier, Robert W.en


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