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dc.date.accessioned2016-08-24T17:54:37Z
dc.date.available2016-08-24T17:54:37Z
dc.date.issued2007-01-09
dc.identifier.urihttp://hdl.handle.net/10919/72546
dc.description.abstractAlteration of voltage input to a voltage regulator output stage from a Vbus regulator stage in a two-stage voltage regulator provides optimal Vbus voltage placement for a wide range of current loads to increase voltage regulator efficiency and is particularly suited to CPUs having power-saving sleep modes of operation. An optimal voltage is selected or developed in response to information concerning operational mode or current consumption of the powered device. As a perfecting feature of one embodiment of the invention in which a discrete Vbus voltage is selected based on operational mode, the selected voltage is adjusted to further optimize the matching of the Vbus voltage placement to the load and provides a continuous range of voltages. In a second embodiment the entire Vbus positioning function is performed in response to current load information. A feed-forward arrangement is provided to avoid transient spikes as the Vbus voltage placement is altered.
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.publisherUnited States Patent and Trademark Office
dc.titleAdaptive bus voltage positioning for two-stage voltage regulators
dc.typePatent
dc.identifier.urlhttp://pimg-fpiw.uspto.gov/fdd/35/613/071/0.pdf
dc.date.accessed2016-08-19
dc.type.dcmitypeText
dc.contributor.assigneeVirginia Tech Intellectual Properties, Inc.
dc.contributor.inventorLee, Fred C.
dc.contributor.inventorXu, Ming Gang
dc.contributor.inventorWei, Jia
dc.date.filed2004-02-20
dc.identifier.applicationnumber10781931
dc.subject.uspc323/266
dc.subject.uspcother323/282
dc.subject.cpcH02M3/156
dc.subject.cpcH02M2001/0019
dc.subject.cpcH02M2001/0032
dc.subject.cpcH02M2001/007
dc.subject.cpcY02B70/16
dc.type.patenttypeutility
dc.identifier.patentnumber7161335


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