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dc.date.accessioned2016-08-24T17:55:03Z
dc.date.available2016-08-24T17:55:03Z
dc.date.issued2011-03-08
dc.identifier.urihttp://hdl.handle.net/10919/72661
dc.description.abstractA method, and system, for reconfiguring an FPGA which has a static region and a dynamic region is provided. The method includes the steps of: (a) providing a dynamic module library having information of predetermined modules; (b) receiving a reconfiguration request external to the FPGA; (c) computing reconfiguration of the FPGA at a predetermined location using predetermined module information from the dynamic module library and the reconfiguration request, and generating reconfigurable partial bitstreams; and (d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration.
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.publisherUnited States Patent and Trademark Office
dc.titleWires on demand: run-time communication synthesis for reconfigurable computing
dc.typePatent
dc.identifier.urlhttp://pimg-fpiw.uspto.gov/fdd/66/028/079/0.pdf
dc.date.accessed2016-08-19
dc.type.dcmitypeText
dc.contributor.assigneeVirginia Tech Intellectual Properties, Inc.
dc.contributor.inventorAthanas, Peter M.
dc.contributor.inventorPatterson, Cameron D.
dc.contributor.inventorDunham, Timothy G.
dc.contributor.inventorBowen, John K.
dc.contributor.inventorRice, Justin D.
dc.contributor.inventorShelburne, Matthew T.
dc.contributor.inventorPletri, Jorge Suris
dc.contributor.inventorGraf, Jonathan P.
dc.date.filed2008-08-27
dc.identifier.applicationnumber12199465
dc.subject.uspc326/41
dc.subject.uspcother326/38
dc.subject.cpcG06F17/5054
dc.type.patenttypeutility
dc.identifier.patentnumber7902866


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