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dc.contributor.authorHsiao, Michael S.en_US
dc.contributor.authorGent, Kelsonen_US
dc.date.accessioned2017-01-02T16:43:18Z
dc.date.available2017-01-02T16:43:18Z
dc.date.issued2016-07en_US
dc.identifier.urihttp://hdl.handle.net/10919/73916
dc.description.abstractFunctional, at-speed vectors continue to provide added value to the testing community as circuit complexity rises. Complex defects may escape traditional scan vectors and thus often require at-speed patterns. However, generation of functional/sequential vectors is an extremely challenging problem. Previous methods rely on formal models of the RTL or calls to gate level ATPG, both of which are computationally expensive, limiting the efficacy of gains made in RTL stimuli generation. In this work, we present an efficient engine for the generation of high quality functional tests at the RTL which are effective for both validation and at-speed defect detection. The proposed method utilizes a rule based, behavioral coverage metric to accurately assess the activation of circuit modules by the generated stimuli. Based on this metric, we are able to effectively generate functional test vectors at the RTL, without additional gate level information, that can achieve a high level of defect coverage and up to an order of magnitude speedup over existing techniques.en
dc.relation.ispartofIEEE Annual Symposium on VLSIen_US
dc.titleFast multi-level test generation at the RTLen_US
dc.typeConference proceeding
dc.description.versionPublished (Publication status)en_US
dc.description.notesYes, full paper (Peer reviewed?)en_US
pubs.organisational-group/Virginia Tech
pubs.organisational-group/Virginia Tech/All T&R Faculty
pubs.organisational-group/Virginia Tech/Engineering
pubs.organisational-group/Virginia Tech/Engineering/COE T&R Faculty
pubs.organisational-group/Virginia Tech/Engineering/Electrical and Computer Engineering


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