New concepts in linear, time invariant model realization using sensitivity functions are presented. These concepts involve approaching the device modeling problem from an error gradient minimization viewpoint. This leads to the attainment of a minimal index of performance function (IP) and, consequently, emulates a desired device model response either in the frequency or time domain.

In the frequency domain the problem of characterizing the AC error gradients for a small signal transistor model is considered. The integral of the weighted squared-error is the IP functional incorporated. It is found that the error gradients all contain a similar expression whose values, when chosen properly, create zero valued gradients and a zero valued (globally minimal) IP functional. Hence a graphical analysis routine based on the similarity expression is developed to provide the advantages listed below:

(i) Simplicity. This technique requires no optimization scheme and completely eliminates computer computation costs.

(ii) Insensitive model. A design scheme is affixed to the graphical analysis scheme so as to yield insensitive voltage and/or current transfer functions; with respect to drifts in hᵢₑ and hₒₑ transistor parameters.

(iii) Basic building block. The small signal model design technique offers a basic building block upon which high frequency model realization techniques, the hybrid pi model for example, can be implemented.

In the time domain a variable structure cascaded building block technique was designed and provides among its main features:

(i) Simplicity. Although an optimization procedure is required in this technique the circuit analysis program incorporated in the negative gradient algorithm is fixed in terms of the topological structure it must analyse. That is, it need not be updated to calculate new gradient terms for a topologically changing structure as is required by previous variable structure modeling techniques.

(ii) Capable of fitting high order responses within a relaxed block by block IP functional. No individual block in the structure may be required to achieve a certain strict IP functional, while the structure in its entirety may achieve the strict functional.

(iii) Direct approach. This device modeling technique offers a concise approach to the modeling problem. The design engineer need only know a device characteristic response in order to approach the problem.

Further research possibilities include characterization of the AC error gradients for the hybrid pi transistor model and possibly a series, parallel, series-parallel, or parallel-series connection would prove even more beneficial than the cascaded block time domain approach.