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dc.contributor.authorLee, Jong-Suk Marken_US
dc.date.accessioned2017-04-06T15:42:40Z
dc.date.available2017-04-06T15:42:40Z
dc.date.issued2010-01-22en_US
dc.identifier.otheretd-02032010-222115en_US
dc.identifier.urihttp://hdl.handle.net/10919/77094
dc.description.abstractHigh computing power and flexibility are important design factors for multimedia and wireless communication applications due to the demand for high quality services and frequent evolution of standards. The ASIC (Application Specific Integrated Circuit) approach provides an area efficient, high performance solution, but is inflexible. In contrast, the general purpose processor approach is flexible, but often fails to provide sufficient computing power. Reconfigurable architectures, which have been introduced as a compromise between the two extreme solutions, have been applied successfully for multimedia and wireless communication applications. In this thesis, we investigated a new coarse-grained reconfigurable architecture called FleXilicon which is designed to execute critical loops efficiently, and is embedded in an SOC with a host processor. FleXilicon improves resource utilization and achieves a high degree of loop level parallelism (LLP). The proposed architecture aims to mitigate major shortcomings with existing architectures through adoption of three schemes, (i) wider memory bandwidth, (ii) adoption of a reconfigurable controller, and (iii) flexible wordlength support. Increased memory bandwidth satisfies memory access requirement in LLP execution. New design of reconfigurable controller minimizes overhead in reconfiguration and improves area efficiency and reconfiguration overhead. Flexible word-length support improves LLP by increasing the number of processing elements executable. The simulation results indicate that FleXilicon reduces the number of clock cycles and increases the speed for all five applications simulated. The speedup ratios compared with conventional architectures are as large as two orders of magnitude for some applications. VLSI implementation of FleXilicon in 65 nm CMOS process indicates that the proposed architecture can operate at a high frequency up to 1 GHz with moderate silicon area.
dc.language.isoen_USen_US
dc.publisherVirginia Techen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectLoop-level parallelismen_US
dc.subjectReconfigurable architectureen_US
dc.subjectarray processingen_US
dc.titleFleXilicon: a New Coarse-grained Reconfigurable Architecture for Multimedia and Wireless Communicationsen_US
dc.typeDissertationen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreePh. D.en_US
thesis.degree.namePh. D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairHa, Dong Samen_US
dc.contributor.committeememberLockhart, Thurmon E.en_US
dc.contributor.committeememberPatterson, Cameron D.en_US
dc.contributor.committeememberReed, Jeffrey Hughen_US
dc.contributor.committeememberSchaumont, Patrick Roberten_US
dc.type.dcmitypeTexten_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-02032010-222115/en_US
dc.date.sdate2010-02-03en_US
dc.date.rdate2016-10-07
dc.date.adate2010-03-23en_US


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