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dc.contributor.authorLee, Hyung K.
dc.contributor.authorHa, Dong S.
dc.date.accessioned2017-09-18T10:11:48Z
dc.date.available2017-09-18T10:11:48Z
dc.date.issued1994-01-01
dc.identifier.citationHyung K. Lee and Dong S. Ha, “An Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuits,” VLSI Design, vol. 2, no. 3, pp. 199-207, 1994. doi:10.1155/1994/71941
dc.identifier.urihttp://hdl.handle.net/10919/79118
dc.description.abstractIn this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, calledSOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into anequivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives testpatterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set sizeare introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANOachieves high SOP fault coverage and short processing time.
dc.format.mimetypeapplication/pdf
dc.language.isoenen_US
dc.publisherHindawien_US
dc.rightsCreative Commons Attribution 4.0 International
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.titleAn Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuitsen_US
dc.typeArticle - Refereed
dc.date.updated2017-09-18T10:11:47Z
dc.description.versionPeer Reviewed
dc.rights.holderCopyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
dc.identifier.doihttps://doi.org/10.1155/1994/71941
dc.type.dcmitypeText


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Creative Commons Attribution 4.0 International
License: Creative Commons Attribution 4.0 International