In this paper, for the first time, the performance analysis of short channel In₀.₅₃Ga₀.₄₇As quantum well (QW) 3-D tri-gate technology with advanced high-κ gate dielectric, TaSiOx is presented. We benchmark the projected performance of sub-10 nm In₀.₅₃Ga₀.₄₇As transistor technology as a function of fin width, fin aspect ratio, and gate length scaling based on present-day lithographic advancement aiding InGaAs QW tri-gate technology as a replacement to Si for sub-10 nm transistor technology. The highly scaled oxide (EOT ∼ 12Å) while retaining superior interfacial properties (Dit ∼ 4 × 10¹¹ cm⁻²eV⁻¹) provides higher ON current for given idle performance. Furthermore, the simulated In₀.₅₃Ga₀.₄₇As tri-gate transistor exhibits superior gate electrostatic control with low OFF-state current (IOFF) ∼ 24.5 nA/μm, peak transconductance (gm) ∼ 2 mS/ μm and high ION/IOFF ratio ∼ 2.3 × 10³, aiding the case of alternate channel transistors for high-speed and low-power CMOS logic.