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dc.contributor.authorBarclay, Daniel Scott
dc.date.accessioned2019-07-03T20:34:05Z
dc.date.available2019-07-03T20:34:05Z
dc.date.issued1987
dc.identifier.urihttp://hdl.handle.net/10919/91158
dc.description.abstractAn automatic method generates tests for circuits described in a hardware description language (HDL). The input description is in a non-procedural subset of VHDL, with a simplified period-oriented timing model. The fault model, based on previous research, includes micro-operation and control statement faults. The test method uses path-tracing, working directly from the circuit description, not a derived graph or table. Artificial intelligence problem-solving techniques of goals and goal solving are used to represent and manipulate sensitization, justification, and propagation requirements. Backtracking is used to recover from incorrect choices. The method is implemented in ProLog, an artificial intelligence language. Results of this experimental ProLog implementation are summarized and analyzed for strengths and weaknesses of the test method. Suggestions are included to counter the weaknesses. A user's manual is included for the experimental implementation.en
dc.format.extentx, 141 leaves
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherVirginia Polytechnic Institute and State University
dc.relation.isformatofOCLC# 16271899
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1987.B371
dc.subject.lcshArtificial intelligence
dc.subject.lcshElectric circuit analysis
dc.subject.lcshHeuristic programming
dc.titleAn automatic test generation method for chip-level circuit descriptions
dc.typeThesis
dc.contributor.departmentElectrical Engineering
dc.description.degreeM.S.
thesis.degree.nameM.S.
thesis.degree.levelmasters
thesis.degree.grantorVirginia Polytechnic Institute and State University
thesis.degree.disciplineElectrical Engineering
dc.type.dcmitypeText


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