Now showing items 1-10 of 14
Test generation for behavioral models with reconvergent fanout and feed-back
(Virginia Tech, 1989-09-15)
<p>In this thesis, new methods to handle reconvergent fanout and feed-back during behavioral level test generation are proposed. These methods have been implemented - into a previously developed automatic test generator. ...
A distributed design rule checker for VLSI layouts
(Virginia Tech, 1990-01-03)
<p>VLSI technology is continually fueling the need for more efficient computer aided design tools. Parallel or distributed processing is a possible solution to this problem. Advances in computer networking have made ...
Automatic verification of VHDL models
(Virginia Tech, 1990-07-07)
<p>Verification of a model describing a hardware system is very important for modeling and simulation purposes. It is necessary to ensure that the model accurately describes the hardware system. A scheme for the automatic ...
Probability of latching single event upset errors in VLSI circuits
(Virginia Tech, 1991-02-05)
The ability of radiation to cause transient faults in space borne as well as ground based computers is well known. with the density of VLSI circuits increasing every year, the probability of an upset by radiation is becoming ...
Process level test generation for VHDL behavioral models
(Virginia Tech, 1994-03-05)
<p> This thesis describes the development of the Process Test Generation (PTG) software for the testing of single-process VHDL behavioral models. The PTG software, along with Hierarchical Behavioral Test Generator (HBTG) ...
A comparative study of electromagnetic & circuit simulation tools for the analysis of microwave circuit discontinuities
(Virginia Tech, 1992)
First-pass success is important for cost-effective Monolithic Microwave and Millimeter-wave Integrated Circuits (MMMICs) since additional iterations to the MMMIC design are costly and take months to complete. In order to ...
Analytical modeling and simulation of bicmos for VLSI circuits
(Virginia Tech, 1990)
Susceptibility evaluation of combational logic in VLSI circuits
(Virginia Tech, 1990)
TENOR: an ATPG for transition faults in combinational circuits
(Virginia Tech, 1994)