Show simple item record

dc.contributor.authorPatel, Hiren Dhanjien_US
dc.date.accessioned2011-08-06T14:42:49Z
dc.date.available2011-08-06T14:42:49Z
dc.date.issued2003-12-03en_US
dc.identifier.otheretd-12052003-151950en_US
dc.identifier.urihttp://hdl.handle.net/10919/9632
dc.description.abstractAs SystemC gains popularity as a System Level Design Language (SLDL) for System-On-Chip (SOC) designs, heterogeneous modelling and efficient simulation become increasingly important. The key in making an SLDL heterogeneous is the facility to express different Models Of Computation (MOC). Currently, all SystemC models employ a Discrete-Event simulation kernel making it difficult to express most MOCs without specific designer guidelines. This often makes it unnatural to express different MOCs in SystemC. For the simulation framework, this sometimes results in unnecessary delta cycles for models away from the Discrete-Event MOC, hindering the simulation performance of the model. Our goal is to extend SystemC's simulation framework to allow for better modelling expressiveness and efficiency for the Synchronous Data Flow (SDF) MOC. The SDF MOC follows a paradigm where the production and consumption rates of data by a function block are known a priori. These systems are common in Digital Signal Processing applications where relative sample rates are specified for every component. Knowledge of these rates enables the use of static scheduling. When compared to dynamic scheduling of SDF models, we experience a noticeable improvement in simulation efficiency. We implement an extension to the SystemC kernel that exploits such static scheduling for SDF models and propose designer style guidelines for modelers to use this extension. The modelling paradigm becomes more natural to SDF which results to better simulation efficiency. We will distribute our implementation to the SystemC community to demonstrate that SystemC can be a heterogeneous SLDL.en_US
dc.format.mediumETDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartthesis_etd2.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectModels Of Computationen_US
dc.subjectSystem Level Modellingen_US
dc.subjectSystemCen_US
dc.subjectHeterogeneous Modellingen_US
dc.subjectDiscrete-Event Simulationen_US
dc.subjectEmbedded Systemsen_US
dc.subjectSynchronous Data Flowen_US
dc.titleHEMLOCK: HEterogeneous ModeL Of Computation Kernel for SystemCen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairShukla, Sandeep K.en_US
dc.contributor.committeememberArmstrong, James R.en_US
dc.contributor.committeememberHsiao, Michael S.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-12052003-151950en_US
dc.date.sdate2003-12-05en_US
dc.date.rdate2003-12-15
dc.date.adate2003-12-15en_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record