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dc.contributor.authorBennett, Sidney Pageen_US
dc.date.accessioned2011-08-06T14:45:02Z
dc.date.available2011-08-06T14:45:02Z
dc.date.issued2003-11-01en_US
dc.identifier.otheretd-01062004-132011en_US
dc.identifier.urihttp://hdl.handle.net/10919/9684
dc.description.abstractThe SCMP processor presents a unique approach to processor design: integrating multiple processors, a network, and memory onto a single chip. The benefits to this design include a reduction in overhead incurred by synchronization, communication, and memory accesses. To properly determine its effectiveness, the SCMP architecture must be exercised under a wide variety of workloads, creating the need for a variety of applications. A compiler can relieve the time spent developing these applications by allowing the use of languages such as C and Fortran. However, compiler development is a research area in its own right, requiring extensive knowledge of the architecture to make good use of its resources. This thesis presents the design and implementation of a compiler for the SCMP architecture. The thesis includes an in-depth analysis of SCMP and the necessary design choices for an effective compiler using the SUIF and MachSUIF toolsets. Two optimizations passes are included in the discussion: partial redundancy elimination and instruction scheduling. While these optimizations are not specific to parallel computing, architectural considerations must still be made to properly implement the algorithms within the SCMP compiler. These optimizations yield an overall reduction in execution time of 15-36%.en_US
dc.format.mediumETDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartsibennet_thesis.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectSUIFen_US
dc.subjectCompiler Designen_US
dc.subjectParallel Computingen_US
dc.subjectOptimizationen_US
dc.subjectMachSUIFen_US
dc.subjectMultithreadingOptimizationen_US
dc.subjectParallel Computingen_US
dc.subjectMultithreadingen_US
dc.titleDesigning a Compiler for a Distributed Memory Parallel Computing Systemen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMSen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.contributor.committeechairBaker, James M. Jr.en_US
dc.contributor.committeememberDavis, Nathaniel J. IVen_US
dc.contributor.committeememberArthur, James D.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-01062004-132011en_US
dc.date.sdate2004-01-06en_US
dc.date.rdate2004-01-22
dc.date.adate2004-01-22en_US


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