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dc.contributor.authorMa, Yunweien
dc.contributor.authorXiao, Mingen
dc.contributor.authorZhang, Ruizheen
dc.contributor.authorWang, Hanen
dc.contributor.authorZhang, Yuhaoen
dc.date.accessioned2020-06-01T19:38:57Zen
dc.date.available2020-06-01T19:38:57Zen
dc.date.issued2019-12-13en
dc.identifier.issn2168-6734en
dc.identifier.urihttp://hdl.handle.net/10919/98655en
dc.description.abstractRecent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges for the first time. In our model, two approaches are proposed to compensate interface charges, by the modulation of the SJ doping or the SJ geometry. Based on our model, an analytical study is conducted for GaN SJ transistors, revealing the design windows and optimal values of doping concentration and pillar width as a function of interface charge density. Finally, TCAD simulation is performed for vertical GaN SJ transistors, which validated our analytical model. Our results show that, with optimal designs, interface charges would only induce small degradation in the performance of GaN SJ devices. However, with the increased interface charge density, the design windows for pillar width and doping concentration become increasingly narrow and the upper limit in the pillar width window reduces quickly. When the interface charge density exceeds similar to 3X10(12) cm(-2), the design window of pillar width completely falls into the sub-micron range, indicating significant difficulties in fabrication. Vertical GaN SJ transistors with interface charges retain great advantages over conventional GaN power transistors, but have narrower design windows and require different design rules compared to ideal GaN SJ devices.en
dc.description.sponsorshipFaculty Startup Fund at Virginia Tech; Virginia Tech Open Access Subvention Funden
dc.format.mimetypeapplication/pdfen
dc.language.isoenen
dc.rightsCreative Commons Attribution 4.0 Internationalen
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.subjectPower electronicsen
dc.subjectpower semiconductor devicesen
dc.subjectsuperjunctionen
dc.subjectinterface chargesen
dc.subjectinterface impuritiesen
dc.subjectgallium nitrideen
dc.subjectsemiconductor device modelingen
dc.subjectdevice simulationen
dc.titleSuperjunction Power Transistors With Interface Charges: A Case Study for GaNen
dc.typeArticle - Refereeden
dc.description.notesThis work was supported in part by the Faculty Startup Fund at Virginia Tech and in part by the Virginia Tech Open Access Subvention Fund. (Yunwei Ma and Ming Xiao contributed equally to this work.)en
dc.title.serialIeee Journal of The Electron Devices Societyen
dc.identifier.doihttps://doi.org/10.1109/JEDS.2019.2959713en
dc.identifier.volume8en
dc.identifier.issue1en
dc.type.dcmitypeTexten
dc.type.dcmitypeStillImageen


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Creative Commons Attribution 4.0 International
License: Creative Commons Attribution 4.0 International