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dc.contributor.authorBucciero, Mark Benjaminen_US
dc.date.accessioned2011-08-06T16:01:41Z
dc.date.available2011-08-06T16:01:41Z
dc.date.issued2004-05-11en_US
dc.identifier.otheretd-06042004-084848en_US
dc.identifier.urihttp://hdl.handle.net/10919/9968
dc.description.abstractCurrent processor designs use additional transistors to add functionality that improves performance. These features tend to exploit instruction level parallelism. However, a point of diminishing returns has been reached in this effort. Instead, these additional transistors could be used to take advantage of thread level parallelism (TLP). This type of parallelism focuses on hundreds of instructions, rather than single instructions, executing in parallel. Additionally, as transistor sizes shrink, the wires on a chip become thinner. Fabricating a thinner wire means increasing the resistance and thus, the latency of that wire. In fact, in the near future, a signal may not reach a portion of the chip in a single clock cycle. So, in future designs, it will be important to limit the length of the wires on a chip. The SCMP parallel computer is a new architecture that is made up of small processing elements, called nodes, which are connected in a 2-D mesh with nearest neighbor connections. Nodes communicate with one another, via message passing, through a network, which uses dimension order worm-hole routing. To support TLP, each node is capable of supporting multiple threads, which execute in a non-preemptive round robin manner. The wire lengths of this system are limited since a node is only connected to its nearest neighbors. This paper focuses on the System C hardware design of the node that gets replicated across the chip. The result is a node implementation that can be used to create a hardware model of the SCMP parallel computer.en_US
dc.format.mediumETDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartmbbthesis.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectsystem on chipen_US
dc.subjectsingle chip computeren_US
dc.subjectSCMPen_US
dc.subjectnodeen_US
dc.subjectProcessoren_US
dc.subjectparallelen_US
dc.titleThe Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computeren_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairBaker, James M. Jr.en_US
dc.contributor.committeememberArmstrong, James R.en_US
dc.contributor.committeememberMartin, Thomas L.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06042004-084848en_US
dc.date.sdate2004-06-04en_US
dc.date.rdate2004-06-18
dc.date.adate2004-06-18en_US


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