Hardware Memory Compression for Large-scale Systems

Abstract

Memory has become an increasingly costly resource for both users and service providers, while also contributing significantly to global energy consumption and environmental impact. Memory compression offers a promising solution to mitigate these costs, as memory values exhibit an average compression ratio of up to 3x. Recent work has proposed enhancing the CPU's memory controller to compress memory values transparently, thereby increasing effective memory capacity—an approach referred to as hardware memory compression. This dissertation focuses on hardware memory compression for large-scale systems. In general, large-scale systems have unique properties: (1) applications are more demanding on address translation, (2) many users execute workloads requesting different amounts of memory concurrently, and (3) these systems have stricter reliability requirements. These properties introduce new challenges when implementing hardware memory compression. This dissertation explores hardware-software co-design to address the challenges. To reduce address translation overhead, we propose selectively compressing cold memory pages while keeping hot pages uncompressed. To enable precise memory allocation, we introduce a novel memory allocation mechanism coupled with a dedicated interface. Finally, this dissertation proposes a novel scheduling scheme that avoids relying on existing speculative-based scheduling which makes the system reliable. Collectively, these works aim to make hardware memory compression deployable in large-scale systems.