Mapping conceptual graphs to primitive VHDL processes

Abstract

This thesis discusses an algorithm for mapping conceptual graphs to primitive VHDL processes. The behavior of each primitive process is stored in the form of a schema. The algorithm identifies concepts in the input referring to MODAS (Modeler's Assistant) process primitives and maps their schemata to the input conceptual graph. The results of the mapping are used to modify the primitive process's VHDL and instantiate a new process. A library of schemata for the primitive processes in MODAS has been developed.

This algorithm has been implemented in the CGVHDL Linker program. It has improved the capability of the CGVHDL Linker to handle more complex design specifications. The algorithm provides the CGVHDL Linker with the ability to interpret a structure in the input conceptual graph. It also eases the burden on the designer who can refer to some components without giving details of their behavior.