Improved pattern growth and reconfiguration methods for a fault- tolerant cellular architecture
| dc.contributor.author | Brighton, Bryan Arthur | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2021-07-22T18:16:19Z | en |
| dc.date.available | 2021-07-22T18:16:19Z | en |
| dc.date.issued | 1987 | en |
| dc.description.abstract | The subject of three dissertations and a thesis written at Va. Tech under the direction of Dr. Gray, has been the development of a fault tolerant parallel architecture. The main thrust of this research has been on distributing the control of the parallel architecture through the use of the ideas behind cellular automata. The control has been distributed, because having a single control unit constitutes a "hard-core," in that a single failure in the control unit can bring down the whole system. The parallel architectures for which these distributed control methods are relevant are described in Chapter I. These architectures include systolic arrays and ensemble architectures, such as Snyder's CHiP computer. It may be possible to extend the same ideas to the distributed control of other architectures, but this has not been investigated here. Chapter II gives the mathematical background of cellular automata on which the control methods are couched. Chapter III describes a new method for growing patterns of control states and analyzes the new method and previous methods. Chapter IV describes the corrections and improvements to Kumar's distributed reconfiguration methods that were found necessary after simulation. Chapter V documents the simulator used to verify the pattern growth and reconfiguration algorithms. The simulator may be easily extended to include solutions to the problems of distributed fault diagnosis and distributed I/0 after the solutions to these problems are fully developed. | en |
| dc.description.degree | M.S. | en |
| dc.format.extent | ix, 216 leaves | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/10919/104325 | en |
| dc.language.iso | en | en |
| dc.publisher | Virginia Polytechnic Institute and State University | en |
| dc.relation.isformatof | OCLC# 17729675 | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.lcc | LD5655.V855 1987.B745 | en |
| dc.subject.lcsh | Parallel processing (Electronic computers) | en |
| dc.title | Improved pattern growth and reconfiguration methods for a fault- tolerant cellular architecture | en |
| dc.type | Thesis | en |
| dc.type.dcmitype | Text | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | M.S. | en |
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