Nguyen, Hieu MinhZhang, FeifeiO'Connell, IvanStaszewski, R. BogdanWalling, Jeffrey S.2023-02-272023-02-272022-011549-7747http://hdl.handle.net/10919/113983The class-D power amplifier (PA) is commonly implemented in CMOS, but its operating frequency is often limited due to the power loss of parasitic capacitances and the lower transition frequency of the the PMOS transistor. In this brief we demonstrate edge-combining frequency-multiplication embedded directly in the output-stage, allowing higher-frequency operation of the class-D PA, while maintaining similar performance to a lower-frequency PA. A 65 nm CMOS prototype achieves output power and system efficiency of 22.3 dBm and 30.2%, respectively. The prototype is tested with a D-BPSK signal and achieves an EVM of 2%-rms. Although the prototype was not embedded with amplitude modulation capability, it can be readily adapted for such operation using switched-capacitor PA techniques.Pages 471-475application/pdfenIn CopyrightCMOS power amplifierArticle - Refereed2023-02-26https://doi.org/10.1109/TCSII.2022.3171495702Walling, Jeffrey [0000-0003-0863-4182]1558-3791