2016-08-242016-08-242007-01-09http://hdl.handle.net/10919/72546Alteration of voltage input to a voltage regulator output stage from a V<sub>bus </sub>regulator stage in a two-stage voltage regulator provides optimal V<sub>bus </sub>voltage placement for a wide range of current loads to increase voltage regulator efficiency and is particularly suited to CPUs having power-saving sleep modes of operation. An optimal voltage is selected or developed in response to information concerning operational mode or current consumption of the powered device. As a perfecting feature of one embodiment of the invention in which a discrete V<sub>bus </sub>voltage is selected based on operational mode, the selected voltage is adjusted to further optimize the matching of the V<sub>bus </sub>voltage placement to the load and provides a continuous range of voltages. In a second embodiment the entire V<sub>bus </sub>positioning function is performed in response to current load information. A feed-forward arrangement is provided to avoid transient spikes as the V<sub>bus </sub>voltage placement is altered.application/pdfen-USAdaptive bus voltage positioning for two-stage voltage regulatorsPatenthttp://pimg-fpiw.uspto.gov/fdd/35/613/071/0.pdf10781931323/266323/282H02M3/156H02M2001/0019H02M2001/0032H02M2001/007Y02B70/167161335