Bhasin, InderpreetTront, Joseph G.2017-09-182017-09-181994-01-01Inderpreet Bhasin and Joseph G. Tront, “Block-Level Logic Extraction from CMOS VLSILayouts,” VLSI Design, vol. 1, no. 3, pp. 243-259, 1994. doi:10.1155/1994/67035http://hdl.handle.net/10919/79117This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level descriptionof a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to thatof a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors,resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be usedto identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to thecircuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logicblocks composed of these gates are then identified. More complex blocks which contain blocks already identifiedare recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It canprovide a connectivity check for a circuit.application/pdfenCreative Commons Attribution 4.0 InternationalArticle - Refereed2017-09-18Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.https://doi.org/10.1155/1994/67035