Frangieh, Tannous2014-03-142014-03-142012-09-28etd-10082012-021855http://hdl.handle.net/10919/29225Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.In CopyrightConfigurable ComputingFPGA ProductivityDesign Assembly FlowElectronic Design AutomationDesign ReuseDissertationhttp://scholar.lib.vt.edu/theses/available/etd-10082012-021855/