Wu, Jia2014-03-142014-03-142000-05-03etd-05102000-11030058http://hdl.handle.net/10919/32468Power electronics building blocks (PEBBs) are standardized building blocks used to integrate power electronics systems. The PEBB approach can achieve low cost, high redundancy, high reliability, high flexibility and easy maintenance for large-scale power electronics systems. This thesis presents the implementation of a 100kW PEBB-based soft-switched bus regulator for an 800V DC distributed power system. The zero current transition (ZCT) soft-switching technique is used to improve the performance of the bus regulator by minimizing switching loss and improving overall efficiency. PEBB modules and a digital control building block are the subsystems of the DC bus regulator. This thesis addresses the design issues at subsystem and system levels. These include: operational principles and design of ZCT PEBB modules; design and implementation of the digital control block, based on DSP and EPLD; and modeling and control design of the DC bus regulator. There are several considerations when using the ZCT soft-switching technique in three-phase applications: the timing of the auxiliary switch gate signals must be arranged differently; there are low-frequency harmonics caused by the pulse width limits; and there is high thermal stress on the resonant capacitors. These issues are resolved by utilizing the sensed phase current information and the design freedom in the PWM modulator. A PWM modulation technique is proposed that can considerably reduce the switching events and further remove the associated loss while keeping THD low. Reduced switching events alleviate the thermal issue of the resonant capacitors. The same modulation technique can avoid the low-frequency harmonics caused by the pulse width limits and double the sampling frequency. The phase current information is used to deal with the control timing issue of the auxiliary switches and to control the three-phase soft-switching operation in order to achieve better efficiency. Additionally, the phase current information is used to implement dead time compensation to reduce THD. The soft-switched DC bus regulator has been tested up to a 100kW power level with 20kHz switching frequency. Experimental results demonstrate that high performance of the DC bus regulator is accomplished in terms of wide control bandwidth, low THD, unity power factor, high efficiency and high power density.In CopyrightRectifierSpace Vector Modulation (SVM)Power Factor Correction (PFC)Power Electronics Building Blocks (PEBB)Soft SwitchingDC Bus RegulatorThesishttp://scholar.lib.vt.edu/theses/available/etd-05102000-11030058/