Heumesser, V.Lai, J. S.Hsieh, H. C.Hsu, J.Yang, C. Y.Chang, E. Y.Liu, C. Y.Chieng, W. H.Hsieh, Y. T.2024-02-262024-02-262023-01-019798350337112https://hdl.handle.net/10919/118159The aim of this paper is to analyze the conventional cascode gate driving to understand the switching transition and to provide a design guide for the GaN HEMT and its associated packaging. A double-pulse tester has been designed and fabricated with minimum parasitic inductance to avoid unnecessary parasitic ringing. The switching behaviors in both turn-on and -off are analyzed through topological study and explained through SPICE simulation. Two different cascode devices were tested to show the impact of threshold voltage and low-voltage Si MOSFET selection.Pages 1-6application/pdfenIn CopyrightConference proceedinghttps://doi.org/10.1109/WiPDAAsia58218.2023.1026190500Lai, Jih [0000-0003-2315-8460]