Morford, Casey Justin2014-03-142014-03-142005-12-15etd-12162005-144728http://hdl.handle.net/10919/36198With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow.enIn CopyrightField programmable gate arraysPartial ReconfigurationVirtex-II ProBitstream ManipulationBitstreamXilinxVirtex-IIDynamic Module ServerThesishttp://scholar.lib.vt.edu/theses/available/etd-12162005-144728/