Griffin, Glenn2014-03-142014-03-141993-04-05etd-04272010-020102http://hdl.handle.net/10919/42309The ability to extract higher level information from a circuit netlist is useful for VLSI layout verification. An extracted gate level description may be used as input to a gate level simulator for analysis or alternatively may be used as input to a rule-based expert system that performs verification checking at a higher level of abstraction. As a VLSI design evolves it is continually checked for correctness. This implies that the extraction of higher level information is a recurring activity and should be performed as efficiently as possible. This paper describes an alternative method that uses intelligence to quicken the extraction process and compares this method's performance to a more common method.iv, 68 leavesBTDapplication/pdfenIn CopyrightLD5655.V851 1993.G754Integrated circuits -- Very large scale integration -- Design and constructionMaster's projecthttp://scholar.lib.vt.edu/theses/available/etd-04272010-020102/