Integration of VHDL simulation and test verification into a Process Model Graph design environment

Dailey, David M.2014-03-142014-03-141994-06-05etd-11242009-020247http://hdl.handle.net/10919/46017This thesis discusses the ability to maintain a consistent design, simulation, and test verification environment by use of the Process Model Graph (PMG) throughout the development process. This ability extends the functionality of the PMG to include the visualization of simulation results and the verification of test paths within the simulation. These ideas have been implemented within a development tool called the Modeler's Assistant. The integration of the test generation environment into the tool is discussed. The design methodology used in creating the simulation environment is also discussed. Other enhancements to increase the abilities of the tool and improve its usefulness to behavioral test generation and verification are also discussed. Many examples of the new extentions to the tool are presented.x, 150 leavesBTDapplication/pdfenIn CopyrightLD5655.V855 1994.D355VHDL (Computer hardware description language) -- Computer simulationVHDL (Computer hardware description language) -- TestingIntegration of VHDL simulation and test verification into a Process Model Graph design environmentThesishttp://scholar.lib.vt.edu/theses/available/etd-11242009-020247/