2016-08-242016-08-242002-08-27http://hdl.handle.net/10919/72454Resistance and parasitic inductance resulting from interconnection of semiconductor chips in power modules are reduced to negligible levels by a robust structure which completely avoids use of wire bonds through use of ball bonding and flip-chip manufacturing processes, possibly in combination with chip scale packaging and hourglass shaped stacked solder bumps of increased compliance and controlled height/shape. Turn-off voltage overshoot is reduced to about one-half or less than a comparable wire bond packaged power module. Hourglass shaped solder bumps provide increased compliance and reliability over much increased numbers of thermal cycles over wide temperature excursions.application/pdfen-USPatenthttp://pimg-fpiw.uspto.gov/fdd/33/420/064/0.pdf9661376174/538257/707257/712257/E21.503257/E23.021257/E23.172361/743361/718361/720361/768H01L23/5385H01L21/563H01L24/11H01L2224/11003H01L2224/13099H01L2224/45124H01L2224/73203H01L2924/00014H01L2924/01006H01L2924/01013H01L2924/01022H01L2924/01029H01L2924/01033H01L2924/01047H01L2924/01078H01L2924/01082H01L2924/01322H01L2924/014H01L2924/10253H01L2924/12036H01L2924/1305H01L2924/13055H01L2924/13091H01L2924/14H01L2924/181H01L2924/19041H01L2924/19043H01L2924/30107H01L2924/3025H01L2924/00H01L2224/486442033