Liu, Jheng-SinClavel, Michael B.Hudait, Mantu K.2019-07-242019-07-242019-01-07http://hdl.handle.net/10919/91972A novel, tunnel field-effect transistor (TFET)-based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET, and TFET) and AL implementations (efficient charge recovery logic, 2N-2N2P, positive feedback adiabatic logic) operating in the ultra-low voltage (0.3 V ≥ VDD ≤ 0.6 V) regime. By incorporating adiabatic logic functionality into standard combinational logic, an 80% reduction in energy/cycle was achieved. A further 80% reduction in energy/cycle was demonstrated by utilizing near broken-gap TFET devices and simultaneous scaling of supply voltage to 0.3 V, resulting in a 96% reduction in energy/cycle as compared to conventional Si CMOS. Extension of operating frequency beyond 10 MHz, coupled with sub-threshold circuit operation, shows the feasibility of TBAL for energy-efficient Internet of Things applications.9 pagesapplication/pdfenIn CopyrightAdiabatic logicFinFETsstrained Ge/InGaAs heterojunctionstunnel field-effect transistorsTBALArticle - Refereedhttps://doi.org/10.1109/jeds.2019.28912047