Qu, Xin2014-03-142014-03-142000-11-28etd-12212000-222112http://hdl.handle.net/10919/36360This thesis develops semi-automated methods to generate testbenches for VHDL models of communication systems. To illustrate the methods, a VHDL model was constructed for the speech-coding channel of the Global System for Mobile Communication (GSM). GSM is the Pan-European digital mobile telephony standard specified by the European Telecommunication Standards Institute (ETSI). This thesis emphasizes the error detection and error correction procedures that form an important part of the standard. First, a test bench template was generated using "Testbench Pro", a waveform generation tool developed by SynaptiCAD. The template includes a random sequence of speech data. A C program was then developed as a user interface to control the simulation procedure. Using the C program, the user can select a test bench template and specify the input test vectors. The C program adds the user's test vectors to the test bench template to create a final VHDL test bench that is ready for simulation. The testing data is then encoded by the GSM encoder models, passed through the noisy channel model that introduces errors into the data stream and, finally, passed through the GSM decoder models which attempt to correct the channel errors. Sophisticated error detection and error correction algorithms are used in the encoder/decoder models to increase the reliability of data transmission over the noisy channel. Finally, the original speech data is compared to the decoder output to detect any remaining bit errors and to evaluate the system performance. The simulation system is semi-automated. The user selects a set of parameters using the C program interface. A testbench is then automatically created and simulated. Two final report files are automatically generated. No user interaction is needed after the initial parameter selection. Several experiments were performed to illustrate the various features of the automated testbench generation system.In CopyrightVHDLGSMViterbiTestbenchThesishttp://scholar.lib.vt.edu/theses/available/etd-12212000-222112/