Hieu Minh NguyenWalling, Jeffrey SeanZhu, AndingStaszewski, Robert Bogdan2022-08-032022-08-032022-040018-9200http://hdl.handle.net/10919/111442This article proposes an interleaving switched-capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge-combining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3x frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves ${ {{P_{ out}}}>21}$ dBm, drain efficiency >36%, and system efficiency >22% while operating in the Ka-band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).application/pdfenCreative Commons Attribution 4.0 InternationalSwitchesRadio frequencyPower generationCapacitorsSwitching circuitsLinearityCapacitanceClass Dclock distributiondigital PA (DPA)edged combining (EC)mm-wave (mmW)power combiningRF digital-to-analog converter (RF-DAC)switched-capacitor power amplifier (SCPA)transmitter (TX)Article - Refereedhttps://doi.org/10.1109/JSSC.2022.31427185741558-173X