Sulistyo, Jos B.Ha, Dong S.2014-06-122014-06-122002-11-01Jos B. Sulistyo and Dong S. Ha, "A New Characterization Method for Delay and Power Dissipation of Standard Library Cells," VLSI Design, vol. 15, no. 3, pp. 667-678, 2002. doi:10.1080/1065514021000012273.1065-514Xhttp://hdl.handle.net/10919/48922A simplified method for characterization of standard library cells based on the linear delay model is presented in this paper. The linear model is chosen as it allows rapid characterization with a modest number of simulations, while achieving acceptable accuracy. All the parameters of cell delays are defined as 50%-to-50% delays, as distinguished from 50%-to-threshold or threshold-to-50% often used in commercial tools. We found that the 50%-to-50% definition of delays is more consistent and leads to closed-form formula. A subset of library cells in a 0.25 mum technology was characterized using the proposed technique. A test circuit was subsequently generated and simulated to determine the accuracy of the proposed characterization method. SPICE simulations on the test circuit show that the timing estimations obtained through the proposed method is accurate to within 5.6%, and the power estimation was accurate to 4.2%, ignoring parasitics on interconnections.application/pdfenCreative Commons Attribution 3.0 UnportedStandard cellCharacterizationTiming modelsLinear modelPowerEstimationSystemsComputer science, hardware & architectureEngineering, electricalArticle - RefereedCopyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.http://www.hindawi.com/journals/vlsi/2002/457569/cta/https://doi.org/10.1080/1065514021000012273