Tiew, Chin-Yaw2014-03-142014-03-141993etd-03042009-040323http://hdl.handle.net/10919/41387In this thesis, several heuristics that aim to improve the performance of parallel fault simulation for synchronous sequential circuits have been investigated. Three heuristics were incorporated into a well known parallel fault simulator called PROOFS and the efficiency of the heuristics were measured in terms of the number of faults simulated in parallel, the number of gate evaluations, and the CPU time. The three heuristics are critical path tracing, dynamic area reduction and a new heuristic called two level simulation. Critical path tracing and dynamic area reduction which have been previously proposed for combinational circuits are extended for synchronous sequential circuits in this thesis. The two level simulation that was investigated in this thesis is designed for sequential circuits. Experimental results show that critical path tracing is the most effective of the three heuristics. In addition to the three heuristics, new fault injection and fault ordering methods were suggested to improve the speed of an efficient fault simulator called HOPE. HOPE, which was developed at Virginia Tech is, an improved version of PROOFS. HOPE_NEW, which incorporates the two heuristics performs better than HOPE in the number of gate evaluations and the CPU time. HOPE_NEW is about 1.13 times faster than HOPE for the ISCAS89 benchmark circuits. For the largest circuit, the speedup is about 40 percent.x, 88 leavesBTDapplication/pdfenIn CopyrightLD5655.V855 1993.T538Electric circuits, ParallelElectric fault location -- Computer simulationFault location (Engineering)Integrated circuits -- Very large scale integration -- TestingThesishttp://scholar.lib.vt.edu/theses/available/etd-03042009-040323/