Perry, Jonathan2014-03-142014-03-142005-04-29etd-07022005-171746http://hdl.handle.net/10919/33871CMOS Technology has advanced for decades under the rule of Moore's law. But all good things must come to an end. Researchers estimate that CMOS will reach a lower limit on feature size within the next 10 to 15 years. In order to assure further progress in the field, new computing architectures must be investigated. These nanoscale architectures are many and varied. It remains to be seen if any will become a legitimate successor to CMOS. Single electron tunneling is a process by which electrons can be trans- ported (tunnel) across a thin insulating surface. A conducting island sepa rated by a pair of quantum tunnel junctions creates a Single Electron Transistor (SET). SETs exhibit higher functionality than traditional MOSFETs, and function best at very small feature sizes, in the neighborhood of 1nm. Many circuits must be developed before SETs can be considered a viable contender to CMOS technology. One important circuit is the Digital to Analog Converter (DAC). DACs are present on many microprocessors and microcontrollers in use today and are necessary in many situations. While other SET circuits have been proposed, including ADCs, no DAC design exists in open literature. We propose three possible SET DAC designs and characterize them with an HSPICE SET simulation model. The first design is a charge scaling architecture similar to what is frequently used in CMOS. The second two designs are based on a current steering architecture, but are unique in their implementation with SETs.In CopyrightSingle Electron TransistorSETDACNanotechnologyThesishttp://scholar.lib.vt.edu/theses/available/etd-07022005-171746/