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Browsing by Author "Bai, Yuming"

Now showing 1 - 2 of 2
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    Method and circuits for reducing dead time and reverse recovery loss in buck regulators
    (United States Patent and Trademark Office, 2004-05-18)
    A buck regulator having a voltage sensor for sensing a voltage reversal caused by freewheeling current from an output inductor in the regulator. Upon sensing a reversed voltage, the voltage sensor triggers a gate controller to turn on a switch in the regulator, and thereby terminate a dead time. The voltage sensor and gate controller are high speed circuits, and therefore can reduce the duration of the dead time. Reducing the dead time duration improves efficiency by reducing the duration of body diode conduction. The dead time can be reduced to less than a turn-on time of the body diode, thereby preventing charge buildup in the body diode, and, consequently, preventing reverse recovery loss in the body diode. The present invention improves electrical conversion efficiency, and allows for increased operating frequency in buck regulators.
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    Optimization of Power MOSFET for High-Frequency Synchronous Buck Converter
    Bai, Yuming (Virginia Tech, 2003-08-28)
    Evolutions in microprocessor technology require the use of a high-frequency synchronous buck converter (SBC) in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency also causes more power loss on MOSFETs. Optimization of the MOSFETs plays an important role in the system performance. Circuit and device modeling is important in understanding the relationship between the device parameters and the power loss. The gate-to-drain charge (Qgd) is studied by a novel nonlinear model and compared with the simulation results. A new switching model is developed, which takes into account the effect of parasitic inductance on the switching process. Another model for dv/dt-induced false triggering-on relates the false-trigger-on voltage with the parasitic elements of the device and the circuits. Some techniques are proposed to reduce the simulation time of FEA in the circuit simulation. Based on this approach, extensive simulations are performed to study the switching performance of the MOSFET with the effect of the parasitic elements. Directed by the analytical models and the experience acquired in the circuit simulation, the MOSFET optimization is realized using FEA. Different optimization algorithms are compared. The experimental results show that the optimized MOSFETs surpass the mainstream commercialized products in both cost and performance.