Browsing by Author "Gray, David T."

Now showing 1 - 2 of 2
  • Thumbnail Image
    Modeling and Characterization of Friction Stir Fabricated Coatings on Al6061 and Al5083 Substrates
    Gray, David T. (Virginia Tech, 2009-12-09)
    We have created a three-dimensional, implicit finite difference model that can accurately calculate temperatures within the bulk of a sample during a friction stir fabrication process. The model was written in Wolfram Mathematica® 7 for Students, and allows for time-efficient calculation of thermal profiles. The non-dimensionality of the model allows for accurate refinement of the temporospatial mesh, and provides portability across material types. The model provides insight as to the mechanism of heat generation by qualifying the fraction of mechanical energy converted to thermal energy for different material types and sample geometries. Finally, our model gives an understanding of the effects of the heat transfer at the boundaries of the workpiece and suggests a backside heat loss localized at the center of the tool due to a decrease in thermal contact resistance. We have explored the effects of processing parameters on the performance of the friction stir fabrication process. The process has four stages; tool insertion, warm-up, bead formation, and steady-state translation. The tool insertion phase is characterized by a rapid increase in system horsepower requirements. During the warm-up phase, the mechanical energy of the rotating tip is converted to thermal energy. Once enough thermal energy has been transferred to the workpiece, the volume between the tip and the workpiece is filled by feedstock material. Finally, the tool is translated under relatively steady-state conditions. The success or failure of the process is dependent on adequate material delivery to the system. The horsepower requirements of the process depend on the material type and the rate of material delivery. We have explored the effect of processing parameters on the microstructure of the processed samples. Optical microscopy shows that the stratification of layers within the weld and the depth of the weld are both dependent on the processing parameters. EBSD analysis coupled with Vicker's microhardness measurements of the processed pieces show that the grain size within the weld nugget is constant over the range of processing parameters available to the system. Data also show that pressure and heat inherent in friction stir processing of strain-hardened Al5083 counteract strengthening of the temper of the alloy.
  • Thumbnail Image
    Optimization of the Process for Semiconductor Device Fabrication in the MicrON 636 Whittemore Cleanroom Facility
    Gray, David T. (Virginia Tech, 2002-12-20)
    The main objective of this work is to develop and optimize a process for the fabrication of basic semiconductor devices in silicon using the Modu-lab toolset in the MicrON 636 Whittemore cleanroom facility. This toolset is designed to work with four-inch silicon wafers, in a class 10000 cleanroom. Early work on this process produced functioning devices, with low yield and little to no process control. Three aspects of the process were therefore selected for optimization in this work. The oxidation of the surface of the silicon wafers could not be made to follow models proposed by and accepted in the literature. By carefully changing the airflow in the oxidation furnace module, the uniformity of the oxide layer and the agreement of the growth with models increases to acceptable levels. Also, the effects of redistribution of dopant species due to growth of the oxide layer and the subsequent thermal processing are examined qualitatively. Phosphorus diffusion in single-crystal silicon has a complex diffusion mechanism involving charged-vacancies, with concentration-dependent diffusion coefficients. It is therefore a complex mathematical problem to model the diffusion of phosphorus from a solid source within the crystal. An empirical model is proposed that accurately predicts the junction depth and sheet resistance of diffused phosphorus layers within the silicon wafer. Throughout the course of the process it is necessary to monitor the characteristics of the wafers to assure proper conditions. A semiconductor parameter analyzer has been created for this purpose. Our system uses a Keithley model 2400 source meter, Signatone probe station and four-point probe stage, and a PC to measure DC I-V electrical characteristics of materials and devices. The measurements of sheet resistance, as well as device characterization of resistors, p-n junction diodes, and nMOSFETs provides feedback about the accuracy of processing steps, as well as a pedagogical tool for illustrating semiconductor device physics and operation.