Browsing by Author "Ha, Dong Sam"

Now showing 1 - 20 of 129
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    Accelerating Hardware Simulation on Multi-cores
    Nanjundappa, Mahesh (Virginia Tech, 2010-05-04)
    Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today's design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes 2/3rd of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of the inherent parallelism present in circuits. However, the discrete-event model of computation requires a global notion of an event-queue, which makes improving its simulation performance via parallelization even more challenging. This work investigates automatic parallelization of simulation algorithms used to simulate hardware models. In particular, we focus on parallelizing the simulation of hardware designs described at the RTL using SystemC/HDL with examples to clearly describe the parallelization. Even though multi-cores and GPUs other parallelism, efficiently exploiting this parallelism with their programming models is not straightforward. To overcome this, we also focus our research on building intelligent translators to map simulation applications onto multi-cores and GPUs such that the complexity of the low-level programming models is hidden from the designers.
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    Advancing Autonomous Structural Health Monitoring
    Grisso, Benjamin Luke (Virginia Tech, 2007-11-27)
    The focus of this dissertation is aimed at advancing autonomous structural health monitoring. All the research is based on developing the impedance method for monitoring structural health. The impedance technique utilizes piezoelectric patches to interrogate structures of interested with high frequency excitations. These patches are bonded directly to the structure, so information about the health of the structure can be seen in the electrical impedance of the piezoelectric patch. However, traditional impedance techniques require the use of a bulky and expensive impedance analyzer. Research presented here describes efforts to miniaturize the hardware necessary for damage detection. A prototype impedance-based structural health monitoring system, incorporating wireless based communications, is fabricated and validated with experimental testing. The first steps towards a completely autonomous structural health monitoring sensor are also presented. Power harvesting from ambient energy allows a prototype to be operable from a rechargeable power source. Aerospace vehicles are equipped with thermal protection systems to isolate internal components from harsh reentry conditions. While the thermal protection systems are critical to the safety of the vehicle, finding damage in these structures presents a unique challenge. Impedance techniques will be used to detect the standard damage mechanism for one type of thermal protection system. The sensitivity of the impedance method at elevated temperatures is also investigated. Sensors are often affixed to structures as a means of identifying structural defects. However, these sensors are susceptible to damage themselves. Sensor diagnostics is a field of study directed at identifying faulty sensors. The influence of temperature on these techniques is largely unstudied. In this dissertation, a model is generated to identify damaged sensors at any temperature. A sensor diagnostics method is also adapted for use in developed hardware. The prototype used is completely digital, so standard sensor diagnostics techniques are inapplicable. A new method is developed to work with the digital hardware.
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    Apply Machine Learning on Cattle Behavior Classification Using Accelerometer Data
    Zhao, Zhuqing (Virginia Tech, 2022-04-15)
    We used a 50Hz sampling frequency to collect tri-axle acceleration from the cows. For the traditional Machine learning approach, we segmented the data to calculate features, selected the important features, and applied machine learning algorithms for classification. We compared the performance of various models and found a robust model with relatively low computation and high accuracy. For the deep learning approach, we designed an end-to-end trainable Convolutional Neural Networks (CNN) to predict activities for given segments, applied distillation, and quantization to reduce model size. In addition to the fixed window size approach, we used CNN to predict dense labels that each data point has an individual label, inspired by semantic segmentation. In this way, we could have a more precise measurement for the composition of activities. Summarily, physically monitoring the well-being of crowded animals is labor-intensive, so we proposed a solution for timely and efficient measuring of cattle’s daily activities using wearable sensors and machine learning models.
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    Area and Power Conscious Rake Receiver Design for Third Generation WCDMA Systems
    Kim, Jina (Virginia Tech, 2003-01-16)
    A rake receiver, which resolves multipath signals corrupted by a fading channel, is the most complex and power consuming block of a modem chip. Therefore, it is essential to design a rake receiver be efficient in hardware and power. We investigated a design of a rake receiver for the WCDMA (Wideband Code Division Multiple Access) system, which is a third generation wireless communication system. Our rake receiver design is targeted for mobile units, in which low-power consumption is highly important. We made judicious judgments throughout our design process to reduce the overall circuit complexity by trading with the performance. The reduction of the circuit complexity results in low power dissipation for our rake receiver. As the first step in the design of a rake receiver, we generated a software prototype in MATLAB. The prototype included a transmitter and a multipath Rayleigh fading channel, as well as a rake receiver with four fingers. Using the software prototype, we verified the functionality of all blocks of our rake receiver, estimated the performance in terms of bit error rate, and investigated trade-offs between hardware complexity and performance. After the verification and design trade-offs were completed, we manually developed a rake receiver at the RT (Register Transfer) level in VHDL. We proposed and incorporated several schemes in the RT level design to enhance the performance of our rake receiver. As the final step, the RT level design was synthesized to gate level circuits targeting TSMC 0.18 mm CMOS technology under the supply voltage of 1.8 V. We estimated the performance of our rake receiver in area and power dissipation. Our experimental results indicate that the total power dissipation for our rake receiver is 56 mW and the equivalent NAND2 circuit complexity is 983,482. We believe that the performance of our rake receiver is quite satisfactory.
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    ATPG and DFT Algorithms for Delay Fault Testing
    Liu, Xiao (Virginia Tech, 2004-06-10)
    With ever shrinking geometries, growing metal density and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are usually unacceptable for large scale designs due to the prohibitive cost of functional test patterns and the difficulty in achieving very high fault coverage. Scan-based delay testing, which could ensure a high delay fault coverage at reasonable development cost, provides a good alternative to the at-speed functional test. This dissertation addresses several key challenges in scan-based delay testing and develops efficient Automatic Test Pattern Generation (ATPG) and Design-for-testability (DFT) algorithms for delay testing. In the dissertation, two algorithms are first proposed for computing and applying transition test patterns using stuck-at test vectors, thus avoiding the need for a transition fault test generator. The experimental results show that we can improve both test data volume and test application time by 46.5% over a commercial transition ATPG tool. Secondly, we propose a hybrid scan-based delay testing technique for compact and high fault coverage test set, which combines the advantages of both the skewed-load and broadside test application methods. On an average, about 4.5% improvement in fault coverage is obtained by the hybrid approach over the broad-side approach, with very little hardware overhead. Thirdly, we propose and develop a constrained ATPG algorithm for scan-based delay testing, which addresses the overtesting problem due to the possible detection of functionally untestable faults in scan-based testing. The experimental results show that our method efficiently generates a test set for functionally testable transition faults and reduces the yield loss due to overtesting of functionally untestable transition faults. Finally, a new approach on identifying functionally untestable transition faults in non-scan sequential circuits is presented. We formulate a new dominance relationship for transition faults and use it to help identify more untestable transition faults on top of a fault-independent method based on static implications. The experimental results for ISCAS89 sequential benchmark circuits show that our approach can identify many more functionally untestable transition faults than previously reported.
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    ATPG based Preimage Computation: Efficient Search Space Pruning using ZBDD
    Chandrasekar, Kameshwar (Virginia Tech, 2003-07-28)
    Preimage Computation is a fundamental step in Formal Verification of VLSI designs. Conventional OBDD-based methods for Formal Verification suffer from spatial explosion, since large designs can blow up in terms of memory. On the other hand, SAT/ATPG based methods are less demanding on memory. But the run-time can be huge for these methods, since they must explore an exponential search space. In order to reduce this temporal explosion of SAT/ATPG based methods, efficient learning techniques are needed. Conventional ATPG aims at computing a single solution for its objective. In preimage computation, we must enumerate all solutions for the target state during the search. Similar sub-problems often occur during preimage computation that can be identified by the internal state of the circuit. Therefore, it is highly desirable to learn from these search-states and avoid repeated search of identical solution/conflict subspaces, for better performance. In this thesis, we present a new ZBDD based method to compactly store and efficiently search previously explored search-states. We learn from these search-states and avoid repeating subsets and supersets of previously encountered search spaces. Both solution and conflict subspaces are pruned based on simple set operations using ZBDDs. We integrate our techniques into a PODEM based ATPG engine and demonstrate their efficiency on ISCAS '89 benchmark circuits. Experimental results show that upto 90% of the search-space is pruned due to the proposed techniques and we are able to compute preimages for target states where a state-of-the-art technique fails.
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    Automotive Lead-Acid Battery State-of-Health Monitoring System
    Kerley, Ross Andrew (Virginia Tech, 2014-09-05)
    This thesis describes the development of a system to continuously monitor the battery in a car and warn the user of an upcoming battery failure. An automotive battery endures enormous strain when it starts the engine, and when it supplies loads without the engine running. Note that the current during a cranking event often exceeds 500 Amperes. Despite the strains, a car battery still typically lasts 4-6 years before requiring replacement. There is often no warning of when a battery should be replaced and there is never a good time for a battery failure. All currently available lead-acid battery monitoring systems use voltage and current sensing to monitor battery impedance and estimate battery health. However, such a system is costly due to the current sensor and typically requires an expert to operate the system. This thesis describes a prototype system to monitor battery state of health and provide advance warning of an upcoming battery failure using only voltage sensing. The prototype measures the voltage during a cranking event and determines if the battery is healthy or not. The voltage of an unhealthy battery will drop lower than a healthy one, and it will not recover as quickly. The major contributions of the proposed research to the field are an algorithm to predict automotive battery state-of-health that is temperature-dependent and a prototype implementation of the algorithm on an ARM processor development board.
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    A Behavioral Test Strategy For Board Level Systems
    Hameed, Qaisar (Virginia Tech, 1999-03-03)
    A digital board typically contains a heterogeneous mixture of chips: microprocessors, memory, control and I/O logic. Different testing techniques are needed for each of these components. To test the whole board, these techniques must be integrated into an overall testing strategy for the board. In this thesis, we have applied a behavioral testing scheme to test the board. Each component chip is tested by observing the behavior of the system in response to the test code, i.e. the component under test is not isolated from the rest of the circuit during test. This obviates the need for the extra hardware used for isolating the chips that is required for structural testing. But this is done at the cost of reduced fault location, although fault detection is still adequate. We have applied the start small approach to behavioral testing. We start by testing a small core of functions. Then, only those functions already tested are used to test the remaining behavior. The grand goal is testing the whole board. This is divided into goals for testing each of the individual chips, which is further subdivided into sub-goals for each of the sub-functions of the board or sub-goals for testing for the most common faults in a component. Each component is tested one by one. Once a component passes, it is put in a passed items set and then can be used in testing the remaining components. Using the start small approach helps isolate the faults to the chip level and thus results in better fault location than the simple behavioral testing scheme in which there is no concept of passed items set and its usage. As an example, this testing approach is applied to a microcontroller based temperature sensor board. This code is run on the VHDL model of the system, and then also on the actual system. For modeling the system in VHDL, Synopsys Smart model library components are used. Faults are injected in the system and then the performance of the strategy is evaluated. This strategy is found to be very effective in detecting internal faults of the chip and locating the faults to the chip level. The interconnection faults are difficult to locate although they are detected in most of the cases. Different scenarios for incorporating this scheme in legacy systems are also discussed.
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    A built-in self-test PLA generator
    Dhawan, Sanjay (Virginia Tech, 1991-01-15)
    In this thesis we studied a BIST PLA generator (BPG) which generates BIST PLA layouts from the personality matrix of PLAs. We studied various BIST PLA designs and selected the design proposed by Treur, Fujiwara and Agarwal to be employed by BPG. The BIST PLA design is known to be effective in area and fault coverage. We modified the original design (which is presented for nMOS PLAs) for CMOS PLAs and added the control circuit. Implementation of BPG was based on MPLA, a PLA generator. Tiles necessary for BIST PLAs were created and added to the existing PLA tiles. The source code of MPLA was modified in order to place proper tiles and generate layouts of BIST PLAs. A circuit was extracted from a BIST PLA generated by BPG and simulated to verify the correctness of BPG. The performance of BIST PLAs generated by BPG was measured in three categories: area overhead, time overhead and fault coverage.
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    CMOS Receiver Design for Optical Communications over the Data-Rate of 20 Gb/s
    Chong, Joseph (Virginia Tech, 2018-06-21)
    Circuits to extend operation data-rate of a optical receiver is investigated in the dissertation. A new input-stage topology for a transimpedance amplifier (TIA) is designed to achieve 50% higher data-rate is presented, and a new architecture for clock recovery is proposed for 50% higher clock rate. The TIA is based on a gm-boosted common-gate amplifier. The input-resistance is reduced by modifying a transistor at input stage to be diode-connected, and therefore lowers R-C time constant at the input and yielding higher input pole frequency. It also allows removal of input inductor, which reduces design complexity. The proposed circuit was designed and fabricated in 32 nm CMOS SOI technology. Compared to TIAs which mostly operates at 50 GHz bandwidth or lower, the presented TIA stage achieves bandwidth of 74 GHz and gain of 37 dBohms while dissipating 16.5 mW under 1.5V supply voltage. For the clock recovery circuit, a phase-locked loop is designed consisting of a frequency doubling mechanism, a mixer-based phase detector and a 40 GHz voltage-controlled oscillator. The proposed frequency doubling mechanism is an all-analog architecture instead of the conventional digital XOR gate approach. This approach realizes clock-rate of 40 GHz, which is at least 50% higher than other circuits with mixer-based phase detector. Implemented with 0.13-μm CMOS technology, the clock recovery circuit presents peak-to-peak clock jitter of 2.38 ps while consuming 112 mW from a 1.8 V supply.
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    A Constant ON-Time 3-Level Buck Converter for Low Power Applications
    Cassidy, Brian Michael (Virginia Tech, 2015-04-22)
    Smart cameras operate mostly in sleep mode, which is light load for power supplies. Typical buck converter applications have low efficiency under the light load condition, primarily from their power stage and control being optimized for heavy load. The battery life of a smart camera can be extended through improvement of the light load efficiency of the buck converter. This thesis research investigated the first stage converter of a car black box to provide power to a microprocessor, camera, and several other peripherals. The input voltage of the converter is 12 V, and the output voltage is 5 V with the load range being 20 mA (100 mW) to 1000 mA (5000 mW). The primary design objective of the converter is to improve light load efficiency. A 3-level buck converter and its control scheme proposed by Reusch were adopted for the converter in this thesis. A 3-level buck converter has two more MOSFETs and one more capacitor than a synchronous buck converter. Q1 and Q2 are considered the top MOSFETs, while Q3 and Q4 are the synchronous ones. The extra capacitor is used as a second power source to supply the load, which is connected between the source of Q1 and the drain of Q2 and the source of Q3 and the drain of Q4. The methods considered to improve light load efficiency are: PFM (pulse frequency modulation) control scheme with DCM (discontinuous conduction mode) and use of Schottky diodes in lieu of the synchronous MOSFETs, Q3 and Q4. The 3-level buck converter operates in CCM for heavy load above 330 mA and DCM for light load below 330 mA. The first method uses a COT (constant on-time) valley current mode controller that has a built in inductor current zero-crossing detector. COT is used to implement PFM, while the zero-crossing detector allows for DCM. The increase in efficiency comes from reducing the switching frequency as the load decreases by minimizing switching and gate driving loss. The second method uses an external current sense amplifier and a comparator to detect when to shut down the gate drivers for Q3 and Q4. Schottky diodes in parallel with Q3 and Q4 carry the load current when the MOSFETs are off. This increases the efficiency through a reduction in switching loss, gate driving loss, and gate driver power consumption. The proposed converter is prototyped using discrete components. LTC3833 is used as the COT valley current mode controller, which is the center of the control scheme. The efficiency of the 3-level buck converter was measured and ranges from 82% to 95% at 100 mW and 5000 mW, respectively. The transient response of the converter shows no overshoot due to a 500 mA load step up or down, and the output voltage ripple is 30 mV. The majority of the loss comes from the external components, which include a D FF (D flip-flop), AND gate, OR gate, current sense chip, comparator, and four gate drivers. The proposed converter was compared to two off-the-shelf synchronous buck converters. The proposed converter has good efficiency and performance when compared to the other converters, despite the fact that the converter is realized using discrete components.
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    Denial-of-Service Attacks on Battery-Powered Mobile Computers
    Krishnaswami, Jayan (Virginia Tech, 2004-01-12)
    A Denial of Service (DoS) attack is an incident in which the user is deprived of the services of a resource he is expected to have. With the increasing reliance on mobile devices like laptops and palmtops, a new type of DoS attack is possible that attacks the batteries of these devices, called "sleep deprivation attacks". The goal of sleep deprivation attacks is to rapidly drain the battery of the mobile devices, rendering the device inoperable long before the expected battery lifetime, thus denying the service the user expects from the mobile device. The purpose of this research is to investigate these types of attacks so that proper defense mechanisms can be put in place before the attacks become a more sophisticated and potent force. This research presents three different possible methods that can be adopted by an attacker to drain the battery of a device i.e. malignant attacks, benign attacks and network service request attacks. These attacks are implemented on a variety of mobile computing platforms like palmtops and a laptop and the corresponding results are presented. Finally, a mathematical model is presented that estimates the battery life of a device based on its power consumption in various power management states and expected usage. This model can also be used to predict the impact of a DoS attack on the battery life of the device under attack.
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    Design and Analysis of a Low-Power Low-Voltage Quadrature LO Generation Circuit for Wireless Applications
    Wang, Shen (Virginia Tech, 2012-08-31)
    The competitive market of wireless communication devices demands low power and low cost RF solutions. A quadrature local oscillator (LO) is an essential building block for most transceivers. As the CMOS technology scales deeper into the nanometer regime, design of a low-power low-voltage quadrature LO still poses a challenge for RF designers. This dissertation investigates a new quadrature LO topology featuring a transformer-based voltage controlled oscillator (VCO) stacked with a divide-by-two for low-power low-voltage wireless applications. The transformer-based VCO core adopts the Armstrong VCO configuration to mitigate the small voltage headroom and the noise coupling. The LO operating conditions, including the start-up condition, the oscillation frequency, the voltage swing and the current consumption are derived based upon a linearized small-signal model. Both linear time-invariant (LTI) and linear time-variant (LTV) models are utilized to analyze the phase noise of the proposed LO. The results indicate that the quality factor of the primary coil and the mutual inductance between the primary and the secondary coils play an important role in the trade-off between power and noise. The guidelines for determining the parameters of a transformer are developed. The proposed LO was fabricated in 65 nm CMOS technology and its die size is about 0.28 mm2. The measurement results show that the LO can work at 1 V supply voltage, and its operation is robust to process and temperature variations. In high linearity mode, the LO consumes about 2.6 mW of power typically, and the measured phase noise is -140.3 dBc/Hz at 10 MHz offset frequency. The LO frequency is tunable from 1.35 GHz to 1.75 GHz through a combination of a varactor and an 8-bit switched capacitor bank. The proposed LO compares favorably to the existing reported LOs in terms of the figure of merit (FoM). More importantly, high start-up gain, low power consumption and low voltage operation are achieved simultaneously in the proposed topology. However, it also leads to higher design complexity. The contributions of this work can be summarized as 1) proposal of a new quadrature LO topology that is suitable for low-power low-voltage wireless applications, 2) an in-depth circuit analysis as well as design method development, 3) implementation of a fully integrated LO in 65 nm CMOS technology for GPS applications, 4) demonstration of high performance for the design through measurement results. The possible future improvements include the transformer optimization and the method of circuit analysis.
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    Design and Analysis of Defect- and Fault-tolerant Nano-Computing Systems
    Bhaduri, Debayan (Virginia Tech, 2007-02-19)
    The steady downscaling of CMOS technology has led to the development of devices with nanometer dimensions. Contemporaneously, maturity in technologies such as chemical self-assembly and DNA scaffolding has influenced the rapid development of non-CMOS nanodevices including vertical carbon nanotube (CNT) transistors and molecular switches. One main problem in manufacturing defect-free nanodevices, both CMOS and non-CMOS, is the inherent variability in nanoscale fabrication processes. Compared to current CMOS devices, nanodevices are also more susceptible to signal noise and thermal perturbations. One approach for developing robust digital systems from such unreliable nanodevices is to introduce defect- and fault-tolerance at the architecture level. Structurally redundant architectures, reconfigurable architectures and architectures that are a hybrid of the previous two have been proposed as potential defect- and fault-tolerant nanoscale architectures. Hence, the design of reliable nanoscale digital systems will require detailed architectural exploration. In this dissertation, we develop probabilistic methodologies and CAD tools to expedite the exploration of defect- and fault-tolerant architectures. These methodologies and tools will provide nanoscale system designers with the capability to carry out trade-off analysis in terms of area, delay, redundancy and reliability. During execution, the next state of a digital system is only dependent on the present state and the digital signals propagate in discrete time. Hence, we have used Markov processes to analyze the reliability of nanoscale digital architectures. Discrete Time Markov Chains (DTMCs) have been used to analyze logic architectures and Markov Decision processes (MDPs) have been used to analyze memory architectures. Since structurally redundant and reconfigurable nanoarchitectures may consist of millions of nanodevices, we have applied state space partitioning techniques and Belief propagation to scale these techniques. We have developed three toolsets based on these Markovian techniques. One of these toolsets has been specifically developed for the architectural exploration of molecular logic systems. The toolset can generate defect maps for isolating defective nanodevices and provide capabilities to organize structurally redundant fault-tolerant architectures with the non-defective devices. Design trade-offs for each of these architectures can be computed in terms of signal delay, area, redundancy and reliability. Another tool called HMAN (Hybrid Memory Analyzer) has been developed for analyzing molecular memory systems. Besides analyzing reliability-redundancy trade-offs using MDPs, HMAN provides a very accurate redundancy-delay trade-off analysis using HSPICE. SETRA (Scalable, Extensible Tool for Reliability Analysis) has been specifically designed for analyzing nanoscale CMOS logic architectures with DTMCs. SETRA also integrates well with current industry-standard CAD tools. It has been shown that multimodal computational models capture the operation of emerging nanoscale devices such as vertical CNT transistors, instead of the bimodal Boolean computational model that has been used to understand the operation of current electronic devices. We have extended an existing multimodal computational model based on Markov Random Fields (MRFs) for analyzing structurally redundant and reconfigurable architectures. Hence, this dissertation develops multiple probabilistic methodologies and tools for performing nanoscale architectural exploration. It also looks at different defect- and fault-tolerant architectures and explores different nanotechnologies.
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    Design and fabrication of Emitter Controlled Thyristor
    Liu, Yin (Virginia Tech, 2001-06-15)
    The Emitter Controlled Thyristor (ECT) is a new MOS-Gated Thyristor (MGT) that combines the ease of a MOS gate control with the superior current carrying capability of a thyristor structure for high-power applications. An ECT is composed of an emitter switch in series with the thyristor, an emitter-short switch in parallel with the emitter junction of the thyristor, a turn-on FET and the main thyristor structure. Numerical analysis shows that the ECT also offers superior high voltage current saturation capability even for high breakdown voltage ratings. Two different ECT structures are investigated in this research from numerical simulations to experimental fabrications. A novel ECT structure that utilizes IGBT compatible fabrication process was proposed. The emitter short FET, emitter switch FET and turn-on FET are all integrated with a high voltage thyristor. Numerical simulation results show that the ECT has a better conductivity modulation than that of the IGBT and at the same time exhibits superior high voltage current saturation capability, superior FBSOA and RBSOA. The technology trade-off between turn-off energy loss and forward voltage drop of the ECT is also better than that of the IGBT because of the stronger conductivity modulation. A novel self-aligned process is developed to fabricate the device. Experimental characteristics of the fabricated ECT devices show that the ECT achieves lower forward voltage drop and superior high voltage current saturation capability. A Hybrid ECT (HECT) structure was also developed in this research work. The HECT uses an external FET to realize the emitter switching function, hence a complicated fabrication issue was separated into two simple one. The cost of the fabrication decreases and the yield increases due to the hybrid integration. Numerical simulations demonstrate the superior on-state voltage drop and high voltage current saturation capability. A novel seven-mask process was developed to fabricate the HECT. Experimental results show that the HECT could achieve the lower forward voltage drop and superior current saturation capability. The resistive switching test was carried out to demonstrate the switching characteristics of the HECT.
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    Design and Fabrication of the Emitter Controlled Thyristor
    Liu, Yin (Virginia Tech, 2001-06-15)
    The Emitter Controlled Thyristor (ECT) is a new MOS-Gated Thyristor (MGT) that combines the ease of a MOS gate control with the superior current carrying capability of a thyristor structure for high-power applications. An ECT is composed of an emitter switch in series with the thyristor, an emitter-short switch in parallel with the emitter junction of the thyristor, a turn-on FET and the main thyristor structure. Numerical analysis shows that the ECT also offers superior high voltage current saturation capability even for high breakdown voltage ratings. Two different ECT structures are investigated in this research from numerical simulations to experimental fabrications. A novel ECT structure that utilizes IGBT compatible fabrication process was proposed. The emitter short FET, emitter switch FET and turn-on FET are all integrated with a high voltage thyristor. Numerical simulation results show that the ECT has a better conductivity modulation than that of the IGBT and at the same time exhibits superior high voltage current saturation capability, superior FBSOA and RBSOA. The technology trade-off between turn-off energy loss and forward voltage drop of the ECT is also better than that of the IGBT because of the stronger conductivity modulation. A novel self-aligned process is developed to fabricate the device. Experimental characteristics of the fabricated ECT devices show that the ECT achieves lower forward voltage drop and superior high voltage current saturation capability. A Hybrid ECT (HECT) structure was also developed in this research work. The HECT uses an external FET to realize the emitter switching function, hence a complicated fabrication issue was separated into two simple one. The cost of the fabrication decreases and the yield increases due to the hybrid integration. Numerical simulations demonstrate the superior on-state voltage drop and high voltage current saturation capability. A novel seven-mask process was developed to fabricate the HECT. Experimental results show that the HECT could achieve the lower forward voltage drop and superior current saturation capability. The resistive switching test was carried out to demonstrate the switching characteristics of the HECT.
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    Design of a High Temperature GaN-Based Variable Gain Amplifier for Downhole Communications
    Ehteshamuddin, Mohammed (Virginia Tech, 2017-02-07)
    The decline of easily accessible reserves pushes the oil and gas industry to explore deeper wells, where the ambient temperature often exceeds 210 °C. The need for high temperature operation, combined with the need for real-time data logging has created a growing demand for robust, high temperature RF electronics. This thesis presents the design of an intermediate frequency (IF) variable gain amplifier (VGA) for downhole communications, which can operate up to an ambient temperature of 230 °C. The proposed VGA is designed using 0.25 μm GaN on SiC high electron mobility transistor (HEMT) technology. Measured results at 230 °C show that the VGA has a peak gain of 27dB at center frequency of 97.5 MHz, and a gain control range of 29.4 dB. At maximum gain, the input P1dB is -11.57 dBm at 230 °C (-3.63 dBm at 25 °C). Input return loss is below 19 dB, and output return loss is below 12 dB across the entire gain control range from 25 °C to 230 °C. The variation with temperature (25 °C to 230 °C) is 1 dB for maximum gain, and 4.7 dB for gain control range. The total power dissipation is 176 mW for maximum gain at 230 °C.
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    Design of a High Temperature GaN-Based VCO for Downhole Communications
    Feng, Tianming (Virginia Tech, 2017-02-20)
    Decreasing reserves of natural resources drives the oil and gas industry to drill deeper and deeper to reach unexploited wells. Coupled with the demand for substantial real-time data transmission, the need for high speed electronics able to operating in harsher ambient environment is quickly on the rise. This paper presents a high temperature VCO for downhole communication system. The proposed VCO is designed and prototyped using 0.25 μm GaN on SiC RF transistor which has extremely high junction temperature capability. Measurements show that the proposed VCO can operate reliably under ambient temperature from 25 °C up to 230 °C and is tunable from 328 MHz to 353 Mhz. The measured output power is 18 dBm with ±1 dB variations over entire covered temperature and frequency range. Measured phase noise at 230 °C is from -121 dBc/Hz to -109 dBc/Hz at 100 KHz offset.
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    Design of a Highly Linear 24-GHz LNA
    Elyasi, Hedieh (Virginia Tech, 2016-07-05)
    The increasing demand for high data rate devices and many applications in short range high speed communication, attract many RF IC designers to work on 24-GHz transceiver design. The Federal Communication Commission (FCC) also dedicates the unlicensed 24-GHz band for industrial, science, and medical applications to overcome the interference in overcrowded communications and have higher output signal power. LNA is the first building of the receiver and is a very critical building block for the overall receiver performance. The total NF and sensitivity of the receiver mainly depends on the LNAs NF that mandates a very low NF LNA design. Depending on its gain, the noise figure of the next stages can relax. However, the high gain of an LNA enforces the next stages to be more linear since they suffer from larger signal at their input stage and can get saturated easily. Apparently, designing high gain, low noise, and highly linear LNA is very stimulating. In this thesis, a wideband LNA with low noise figure and high linearity has been designed in 8XP 0.13-um SiGe BiCMOS IBM technology. The highlight of this design is proposing the peaking technique, which results in considerable linearity improvement. Loading the LNA with class AB amplifier, power gain experiences a peaking in high input signal swing levels. The next stager after the LNA is the buffer to provide isolation between the LNA and mixer, and also avoid loading of the LNA from the mixer. Instead of using popular emitter follower architecture, another circuit is proposed to have higher gain and linearity. This buffer has two separate out of phase inputs, coming from the LNA and are combined constructively at the output of the buffer. Since the frequency of this design is high, electromagnetic (EM) simulation for pads, interconnects, transmission lines, inductors, and coplanar transmission lines has been completed using Sonnet cad tool to consider all the parasitic and coupling effects. Considering all the EM effects, the LNA has 15 dB gain with 2.9 dB NF and -8.8 dBm input 1-dB compression point. The designed LNA is wideband, covering the frequency range of 12-GHz to 31-GHz. However, the designed LNA, has the capability of having higher gain at the expense of lower linearity and narrower frequency band using different control voltage. As an example peak gain of 29.3 dB at the 3-dB frequency range of 23.8 to 25.8-GHz can be achieved, having 2.3 dB noise figure and -17 dBm linearity.
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    Design of a Low Power Delta Sigma Modulator for Analog to Digital Conversion
    Itskovich, Mikhail (Virginia Tech, 2003-09-01)
    The growing demand of “System on a Chip” applications necessitates integration of multiple devices on the same chip. Analog to Digital conversion is essential to interfacing digital systems to external devices such as sensors. This presents a difficulty since high precision analog devices do not mix well with high speed digital circuits. The digital environment constraints put demand on the analog portion to be resource efficient and noise tolerant at the same time. Even more demanding, Analog to Digital converters must consume a small amount of power since “System on a Chip” circuits often target portable applications. Analog to digital conversion based on Delta Sigma modulation offers an optimal solution to the above problems. It is based on digital signal processing theory and offers benefits such as small footprint, high precision, noise de-sensitivity, and low power consumption. This thesis presents a methodology for designing low power Delta Sigma modulators using a combination of modern circuit design techniques. The developed techniques have resulted in several modulators that satisfy the initial design parameters. We applied this method to design three different modulators in the 0.35um digital CMOS technology with a 3.3V supply voltage. A first order Self-Referenced modulator has a resolution of 8 bits and the lowest power consumption at 75 uW. The most successful design is the second order Self Referenced modulator that produces 12 bits of resolution with a power consumption of 87 uW. A second order Floating Gate modulator possesses features for high noise rejection, and produces 10 bits of resolution while consuming 276 uW. It is concluded that self-referenced modulators dissipate less power and offer higher performance as compared more complicated circuits such as the floating gate modulator.