Browsing by Author "Jiao, Yang"

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    Coupled inductor for interleaved multi-phase three-level DC-DC converters
    (United States Patent and Trademark Office, 2019-08-27)
    Output current ripple is reduced in a three-level DC-DC power converter by connecting a plurality of phase legs in parallel between a source of input power and an output of the power converter and conducting power from the source of input power to the power converter output in an interleaved manner. The large current that results from such interleaved operation is reduced to acceptable levels, potentially less than the output current ripple of the power converter by providing inversely coupled inductors having a mutual inductance preferably greater than the inductor of the power converter in respective phase legs and in series in the circulating current path to avoid any need to increase the power converter inductance due to the circulating current. The inductor and inversely coupled inductors are preferably integrated into a single magnetic element of compact design.
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    High Power High Frequency 3-level NPC Power Conversion System
    Jiao, Yang (Virginia Tech, 2015-09-25)
    The high penetration of renewable energy and the emerging concept of micro-grid system raises challenges to the high power conversion techniques. Multilevel converter plays the key role in such applications and is studied in detail in the dissertation. The topologies and modulation techniques for multilevel converter are categorized at first by a thorough literature survey. The pros and cons for various multilevel topologies and modulation techniques are discussed. The 3-level neutral point clamped (NPC) topology is selected to build a 200kVA, 20 kHz power conversion system. The modularized phase leg building block of the converter is carefully designed to achieve low loss and stress for high frequency and high power operation. The switching characteristics for all the commutation loops of 3-level phase leg are evaluated by double pulse tests. The switching performance is optimized for loss and stress tradeoff. A detailed loss model is built for system loss distribution and loss breakdown calculation. Loss and stress for the phase leg and 3-phase system are quantified at all power factors. The space vector modulation (SVM) for 3-level NPC converter is investigated to achieve loss reduction, neutral voltage balance and noise reduction. The loss model and simulation model provides a quantitative analysis for loss and neutral voltage ripple tradeoff. An improved SVM method is proposed to reduce NP imbalance and switching loss simultaneously. This method also ensures an evenly distributed device loss in each phase leg and gives a constant system efficiency under different power factors. Based on the improved modulation strategy, a new modulation scheme is then proposed with largely reduced conduction loss and switching stress. Moreover, the device loss and stress distribution on a phase leg is more even. This scheme also features on the simplified implementation. The improved switching characteristics for the proposed method are verified by double pulse tests. Also the system loss breakdown and the phase leg loss distribution analysis shows the loss reduction and redistribution result. The harmonic filter for the grid interface converter is designed with LCL topology. A detailed inductor current ripple analysis derives the maximum inductor current ripple and the ripple distribution in a line cycle. The inverter side inductor is designed with the optimum loss and size trade-off. The grid side inductor is designed based on grid code attenuation requirement. Different damping circuits for LCL filter are evaluated in detail. The filter design is verified by both simulation and hardware experiment. The average model for the 3-level NPC converter and its equivalent circuit is derived with the consideration of damping circuit in both ABC and d-q frame. The modeling and control loop design is verified by transfer function measurement on real hardware. The control loops design is also tested and verified on real hardware. The interleaved DC/DC chopper is introduced at last. The different interleaving methods and their current ripple are analyzed in detail with the coupled and non-coupled inductor. An integrated coupled inductor based on 3-dimentional core structure is proposed to achieve high power density and provide both CM and DM impedance for the inductor current and output current.