VTechWorks Repository :: Browsing by Author "Jones, Mark T."

Browsing by Author "Jones, Mark T."

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Activity Recognition Processing in a Self-Contained Wearable System
Chong, Justin Brandon (Virginia Tech, 2008-09-12)
Electronic textiles provide an effective platform to contain wearable computing elements, especially components geared towards the application of activity recognition. An activity recogni tion system built into a wearable textile substrate can be utilized in a variety of areas including health monitoring, military applications, entertainment, and fashion. Many of the activity recognition and motion capture systems previously developed have several drawbacks and limitations with regard to their respective designs and implementations. Some such systems are often times expensive, not conducive to mass production, and may be difficult to calibrate. An effective system must also be scalable and should be deployable in a variety of environments and contexts. This thesis presents the design and implementation of a self-contained motion sensing wearable electronic textile system with an emphasis toward the application of activity recognition. The system is developed with scalability and deployability in mind, and as such, utilizes a two-tier hierarchical model combined with a network infrastructure and wireless connectivity. An example prototype system, in the form of a jumpsuit garment, is presented and is constructed from relatively inexpensive components and materials.
Activity Recognition using Singular Value Decomposition
Jolly, Vineet Kumar (Virginia Tech, 2006-08-08)
A wearable device that accurately records a user's daily activities is of substantial value. It can be used to enhance medical monitoring by maintaining a diary that lists what a person was doing and for how long. The design of a wearable system to record context such as activity recognition is influenced by a combination of variables. A flexible yet systematic approach for building a software classification environment according to a set of variables is described. The integral part of the software design is the use of a unique robust classifier that uses principal component analysis (PCA) through singular value decomposition (SVD) to perform real-time activity recognition. The thesis describes the different facets of the SVD-based approach and how the classifier inputs can be modified to better differentiate between activities. This thesis presents the design and implementation of a classification environment used to perform activity detection for a wearable e-textile system.
An Ambulatory Monitoring Algorithm to Unify Diverse E-Textile Garments
Blake, Madison Thomas (Virginia Tech, 2014-03-11)
In this thesis, an activity classification algorithm is developed to support a human ambulatory monitoring system. This algorithm, to be deployed on an e-textile garment, represents the enabling step in creating a wide range of garments that can use the same classifier without having to re-train for different sensor types. This flexible operation is made possible by basing the classifier on an abstract model of the human body that is the same across all sensor types and subject bodies. In order to support low power devices inherent for wearable systems, the algorithm utilizes regular expressions along with a tree search during classification. To validate the approach, a user study was conducted using video motion capture to record subjects performing a variety of activities. The subjects were randomly placed into two groups, one used to generate the activities known by the classifier and another to be used as observation to the classifier. These two sets were used to gain insight on the performance of the algorithm. The results of the study demonstrate that the algorithm can successfully classify observations, so as long as precautions are taken to prevent the activities known by the classifier to become too large. It is also shown that the tree search performed by the classification can be utilized to partially classify observations that would otherwise be rejected by the classifier. The user study additionally included subjects that performed activities purely used for observations to the classifier. With this set of recordings, it was demonstrated that the classifier does not over-fit and is capable of halting the classification of an observation.
Analysis of a self-contained motion capture garment for e-textiles
Lewis, Robert Alan (Virginia Tech, 2011-05-04)
Wearable computers and e-textiles are becoming increasingly widespread in today's society. Motion capture is one of the many potential applications for on-body electronic systems. Previous work has been performed at Virginia Tech's E-textiles Laboratory to design a framework for a self-contained loose fit motion capture system. This system gathers information from sensors distributed throughout the body on a "smart" garment. This thesis presents the hardware and software components of the framework, along with improvements made to it. This thesis also presents an analysis of both the on-body and off-body network communication to determine how many sensors can be supported on the garment at a given time. Finally, this thesis presents a method for determining the accuracy of the smart garment and shows how it compares against a commercially available motion capture system.
An Analysis of an Interrupt-Driven Implementation of the Master-Worker Model with Application-Specific Coprocessors
Hickman, Joseph (Virginia Tech, 2007-11-12)
In this thesis, we present a versatile parallel programming model composed of an individual general-purpose processor aided by several application-specific coprocessors. These computing units operate under a simplification of the master-worker model. The user-defined coprocessors may be either homogeneous or heterogeneous. We analyze system performance with regard to system size and task granularity, and we present experimental results to determine the optimal operating conditions. Finally, we consider the suitability of this approach for scientific simulations — specifically for use in agent-based models of biological systems.
An Application Framework for a Power-Aware Processor Architecture
Mandlekar, Anup Shrikant (Virginia Tech, 2012-08-07)
The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency, was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software applications to test the architecture performance. The application framework is integrated with the prior automation framework bringing software applications at the right level of abstraction. The processor architecture design is made flexible and scalable, making it suitable for a wide range of applications. Additionally, an embedded flash memory based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory.
An Architecture for Electronic Textiles
Jones, Mark T.; Martin, Thomas L.; Sawyer, Braden (ICST, 2008)
This paper makes a case for a communication architecture for electronic textiles (e-textiles). The properties and re- quirements of e-textile garments are described and analyzed. Based on these properties, the authors make a case for em- ploying wired, digital communication as the primary on- garment communication network. The implications of this design choice for the hardware architecture for e-textiles are discussed.
Architecture-Independent Design for Run-Time Reconfigurable Custom Computing Machines
Hudson, Rhett Daniel (Virginia Tech, 2000-07-20)
The configurable computing research community has provided a wealth of evidence that computational platforms based on FPGA technology are capable of cost-effectively accelerating certain kinds of computations. One actively growing area in the research community examines the benefits to computation that can be gained by reconfiguring the FPGAs in a system during the execution of an application. This technique is commonly referred to as run-time reconfiguration. Widespread acceptance of run-time reconfigurable custom computing depends upon the existence of high-level automated design tools. Given the wide variety of available platforms and the rate that the technology is evolving, a set of architecturally independent tools that provide the ability to port applications between different architectures will allow application-based intellectual property to be easily migrated between platforms. A Java implementation of such a toolset, called Janus, is presented and analyzed here. In this environment, developers create a Java class that describes the structural behavior of an application. The design framework allows hardware and software modules to be freely intermixed. During the compilation phase of the development process, the Janus tools analyze the structure of the application and adapt it to the target architecture. Janus is capable of structuring the run-time behavior of an application to take advantage of the resources available on the platform. Examples of applications developed using the toolset are presented. The performance of the applications is reported. The retargeting of applications for multiple hardware architectures is demonstrated.
Architectures for e-Textiles
Nakad, Zahi Samir (Virginia Tech, 2003-12-10)
The huge advancement in the textiles industry and the accurate control on the mechanization process coupled with cost-effective manufacturing offer an innovative environment for new electronic systems, namely electronic textiles. The abundance of fabrics in our regular life offers immense possibilities for electronic integration both in wearable and large-scale applications. Augmenting this technology with a set of precepts and a simulation environment creates a new software/hardware architecture with widely useful implementations in wearable and large-area computational systems. The software environment acts as a functional modeling and testing platform, providing estimates of design metrics such as power consumption. The construction of an electronic textile (e-textile) hardware prototype, a large-scale acoustic beamformer, provides a basis for the simulator and offers experience in building these systems. The contributions of this research focus on defining the electronic textile architecture, creating a simulation environment, defining a networking scheme, and implementing hardware prototypes.
Automatically Locating Sensor Position on an E-textile Garment Via Pattern Recognition
Love, Andrew R. (Virginia Tech, 2009-09-30)
Electronic textiles are a sound platform for wearable computing. Many applications have been devised that use sensors placed on these textiles for fields such as medical monitoring and military use or for display purposes. Most of these applications require that the sensors have known locations for accurate results. Activity recognition is one application that is highly dependent on knowledge of the sensor position. Therefore, this thesis presents the design and implementation of a method whereby the location of the sensors on the electronic textile garments can be automatically identified when the user is performing an appropriate activity. The software design incorporates principle component analysis using singular value decomposition to identify the location of the sensors. This thesis presents a method to overcome the problem of bilateral symmetry through sensor connector design and sensor orientation detection. The scalability of the solution is maintained through the use of culling techniques. This thesis presents a flexible solution that allows for the fine-tuning of the accuracy of the results versus the number of valid queries, depending on the constraints of the application. The resulting algorithm is successfully tested on both motion capture and sensor data from an electronic textile garment.
Autonomous Computing Systems
Steiner, Neil Joseph (Virginia Tech, 2008-03-27)
This work discusses autonomous computing systems, as implemented in hardware, and the properties required for such systems to function. Particular attention is placed on shifting the associated complexity into the systems themselves, and making them responsible for their own resources and operation. The resulting systems present simpler interfaces to their environments, and are able to respond to changes within themselves or their environments with little or no outside intervention. This work proposes a roadmap for the development of autonomous computing systems, and shows that their individual components can be implemented with present day technology. This work further implements a proof-of-concept demonstration system that advances the state-of-the-art. The system detects activity on connected inputs, and responds to the conditions without external assistance. It works from mapped netlists, that it dynamically parses, places, routes, configures, connects, and implements within itself, at the finest granularity available, while continuing to run. The system also models itself and its resource usage, and keeps that model synchronized with the changes that it undergoes—a critical requirement for autonomous systems. Furthermore, because the system assumes responsibility for its resources, it is able to dynamically avoid resources that have been masked out, in a manner suitable for defect tolerance.
Balancing Performance, Area, and Power in an On-Chip Network
Gold, Brian (Virginia Tech, 2003-07-23)
Several trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the increasing gap between processor and off-chip memory speeds has constrained performance of memory-intensive applications. The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network removes global, ad-hoc wiring that limits scalability and introduces design complexity. However, routing data through general purpose interconnection networks can come at the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. Understanding the impact architectural decisions have on cost and performance will aid in the eventual adoption of general purpose interconnects. This thesis covers the design and analysis of the on-chip network and its integration with the SCMP system. The result of these efforts is a framework for analyzing on-chip interconnection networks that considers network performance, circuit area, and power consumption.
Cellular Automata for Structural Optimization on Recongfigurable Computers
Hartka, Thomas Ryan (Virginia Tech, 2004-05-12)
Structural analysis and design optimization is important to a wide variety of disciplines. The current methods for these tasks require significant time and computing resources. Reconfigurable computers have shown the ability to speed up many applications, but are unable to handle efficiently the precision requirements for traditional analysis and optimization techniques. Cellular automata theory provides a method to model these problems in a format conducive to representation on a reconfigurable computer. The calculations do not need to be executed with high precision and can be performed in parallel. By implementing cellular automata simulations on a reconfigurable computer, structural analysis and design optimization can be performed significantly faster than conventional methods.
Chemotaxis in Densely Populated Tissue Determines Germinal Center Anatomy and Cell Motility: A New Paradigm for the Development of Complex Tissues
Hawkins, Jared B.; Jones, Mark T.; Plassmann, Paul E.; Thorley-Lawson, David A. (PLOS, 2011-12-01)
Germinal centers (GCs) are complex dynamic structures that form within lymph nodes as an essential process in the humoral immune response. They represent a paradigm for studying the regulation of cell movement in the development of complex anatomical structures. We have developed a simulation of a modified cyclic re-entry model of GC dynamics which successfully employs chemotaxis to recapitulate the anatomy of the primary follicle and the development of a mature GC, including correctly structured mantle, dark and light zones. We then show that correct single cell movement dynamics (including persistent random walk and inter-zonal crossing) arise from this simulation as purely emergent properties. The major insight of our study is that chemotaxis can only achieve this when constrained by the known biological properties that cells are incompressible, exist in a densely packed environment, and must therefore compete for space. It is this interplay of chemotaxis and competition for limited space that generates all the complex and biologically accurate behaviors described here. Thus, from a single simple mechanism that is well documented in the biological literature, we can explain both higher level structure and single cell movement behaviors. To our knowledge this is the first GC model that is able to recapitulate both correctly detailed anatomy and single cell movement. This mechanism may have wide application for modeling other biological systems where cells undergo complex patterns of movement to produce defined anatomical structures with sharp tissue boundaries.
Classifier for Activities with Variations
Younes, Rabih; Jones, Mark T.; Martin, Thomas L. (MDPI, 2018-10-18)
Most activity classifiers focus on recognizing application-specific activities that are mostly performed in a scripted manner, where there is very little room for variation within the activity. These classifiers are mainly good at recognizing short scripted activities that are performed in a specific way. In reality, especially when considering daily activities, humans perform complex activities in a variety of ways. In this work, we aim to make activity recognition more practical by proposing a novel approach to recognize complex heterogeneous activities that could be performed in a wide variety of ways. We collect data from 15 subjects performing eight complex activities and test our approach while analyzing it from different aspects. The results show the validity of our approach. They also show how it performs better than the state-of-the-art approaches that tried to recognize the same activities in a more controlled environment.
Collaborative Scheduling and Synchronization of Distributable Real-Time Threads
Fahmy, Sherif Fadel (Virginia Tech, 2010-05-05)
In this dissertation, we consider the problem of scheduling and synchronization of distributable real-time threads --- Real-Time CORBA's first-class abstraction for programming real-time, multi-node sequential behaviors. Distributable real-time threads can be scheduled, broadly, using two paradigms: node independent scheduling, in which nodes independently construct thread schedules, based on node-level decomposition of distributable thread (or DT) scheduling parameters, and collaborative scheduling, in which nodes collaborate to construct system-wide thread schedules, which may or may not involve scheduling parameter decomposition. While significant literature exists on node independent scheduling, little is known about collaborative scheduling and its concomitant tradeoffs. We design three collaborative scheduling algorithms, called ACUA, QBUA, and DQBUA. ACUA uses theory of consensus and QBUA uses theory of quorums for distributable thread schedule construction. DQBUA extends QBUA with lock-based, local and distributed concurrency control. The algorithms consider a model where distributable threads arrive arbitrarily, have time/utility function time constraints, access resources in an arbitrary way (e.g., arbitrary lock acquire/release order, arbitrary nestings), and are subject to arbitrary node crash failures and message losses. We analytically establish several properties of the algorithms including probabilistic end-to-end termination time satisfactions, timeliness optimality during underloads, bounded exception handling time, and correctness of the algorithms in partially synchronous systems. We implement distributable real-time threads in the Linux kernel as a first-class programming and scheduling abstraction. The resulting kernel, called ChronOS, provides application interfaces for creating and manipulating distributable threads, as well as kernel interfaces and mechanisms for scheduling them (using both independent and collaborative approaches). ChronOS also has failure detector mechanisms for detecting and recovering from distributable thread failures. We implement the proposed scheduling algorithms and their competitors in ChronOS and compare their behavior. Our studies reveal that the collaborative scheduling algorithms are superior to independent scheduling algorithms for certain thread sets, in particular, when thread sections have significantly varying execution time. This variability, especially if the variability is not consistent among the threads, may cause each node to make conflicting decisions in the absence of global information. We observe that collaborative schedulers outperform independent schedulers (e.g., EDF augmented with PIP) in terms of accrued utility by as much as 75%. We identify distributed dependencies as one of the major sources of overhead in collaborative scheduling. In particular, the cost of distributed lock-based concurrency control (e.g., lock management, distributed deadlock detection/resolution) can significantly reduce the problem space for which collaborative scheduling is beneficial. To mitigate this, we consider the use of software transactional memory (or STM), an optimistic, non-blocking synchronization alternative to lock-based concurrency control which has been extensively studied in non real-time contexts. We consider distributable real-time threads with STM concurrency control, and develop techniques for analyzing and bounding their end-to-end response times on distributed single-processor and distributed multiprocessor systems. We also develop contention management techniques, a key component of STM, which are driven by threads' real-time scheduling parameters, and establish their tradeoffs against non-real-time contention managers.
Context Switching Strategies in a Run-Time Reconfigurable system
Puttegowda, Kiran (Virginia Tech, 2002-04-16)
A distinctive feature of run-time reconfigurable systems is the ability to change the configuration of programmable resources during execution. This opens a number of possibilities such as virtualisation of computational resources, simplified routing and in certain applications lower power. Seamless run-time reconfiguration requires rapid configuration. Commodity programmable devices have relatively long configuration time, which makes them poor candidates for run-time reconfigurable systems. Reducing this reconfiguration time to the order of nano seconds will enable rapid run-time reconfiguration. Having multiple configuration planes and switching between them while processing data is one approach towards achieving rapid reconfiguration. An experimental context switching programmable device, called the Context Switching Reconfigurable Computer (CSRC), has been created by BAE Systems, which provided opportunities to explore context-switching strategies for run-time reconfigurable systems. The work presented here studies this approach for run-time reconfiguration, by applying the concepts to develop applications on a context switching reconfigurable system. The work also discusses the advantages and disadvantages of such an approach and ways of leveraging the concept for efficient computing.
Correlating Computer User Stress and Performance in Both Preferred and Non-preferred Modalities
Castles, Ricky Thomas (Virginia Tech, 2006-05-08)
Most computer interfaces are designed in a one-size-fits-all fashion, which does not account for individual differences in abilities and preferences. Some computer users thrive with one software application while another user may struggle to use the same software. Some people tend to perform very well amidst distraction whereas others have a difficult time concentrating on a primary task when distracting agents are present. Much work has been done in quantifying a person's performance, but it has typically been difficult to quantify how difficult a task was for a person to perform. This thesis looks into the stress exhibited by various computer users while performing tasks in both their preferred and non-preferred modalities. The paper surveys the current physiological methods for analyzing human stress and delineates the hardware and software design and implementation of some of these methods. The physiological data-collecting hardware and software were deployed to collect physiological samples from test subjects engaging in memorization and recollection tasks in both an undistracted and a distracted setting. An analysis of the data shows the correlation between preferred modality and performance of tasks in that modality and other modalities. This analysis also shows the correlation between user arousal level and performance with and without distraction. Individual differences are considered by normalizing the physiological data collected for each subject prior to comparison with other subjects. The work presented herein gives insight into the individual differences of various types of computer users and is a precursor to work in adaptive user interface technology.
A Cross Platform Method for FPGA Integrity Checking
Benz, Matthew Aaron (Virginia Tech, 2007-08-30)
As embedded systems continue to evolve and the number of applications they support continues to increase, so does the diversity of the hardware they employ. As a result, the Field Programmable Gate Arrays (FPGAs), which have become fundamental elements in their design, have advanced in size and complexity as well. Because of this, it is now impossible to ignore the security implications that accompany such a progression. It is then not only important to prevent malicious attacks targeted at FPGAs from extracting the intellectual property contained in their configuration, but to now extend the research in this field by providing a cross-platform solution capable of securing the integrity of FPGA configurations at run-time. Today, there exist myriad attack strategies employed against FPGAs, the majority of which are seen in the form of semi-invasive attacks. These attacks manipulate the configuration of an FPGA and typically modify the state of the transistors that make up said configuration. This thesis introduces a multi-platform method for checking the integrity of an FPGA's configuration. The details of the system's design and implementation are discussed in addition to the analysis of the design trade-offs met when employing the system across multiple FPGA families. The system is implemented entirely in hardware and resides on-chip, providing an FPGA the ability to act as private entity capable of successfully detecting when it has been maliciously attacked.
Design and Analysis of Four Architectures for FPGA-Based Cellular Computing
Morgan, Kenneth J. (Virginia Tech, 2004-10-19)
The computational abilities of today's parallel supercomputers are often quite impressive, but these machines can be impractical for some researchers due to prohibitive costs and limited availability. These researchers might be better served by a more personal solution such as a "hardware acceleration" peripheral for a PC. FPGAs are the ideal device for the task: their configurability allows a problem to be translated directly into hardware, and their reconfigurability allows the same chip to be reprogrammed for a different problem. Efficient FPGA computation of parallel problems calls for cellular computing, which uses an array of independent, locally connected processing elements, or cells, that compute a problem in parallel. The architecture of the computing cells determines the performance of the FPGA-based computer in terms of the cell density possible and the speedup over conventional single-processor computation. This thesis presents the design and performance results of four computing-cell architectures. MULTIPLE performs all operations in one cycle, which takes the least amount of time but requires the most chip area. BIT performs all operations bit-serially, which takes a long time but allows a large cell density. The two other architectures, SINGLE and BOOTH, lie within these two extremes of the area/time spectrum. The performance results show that MULTIPLE provides the greatest speedup over common calculation software, but its usefulness is limited by its small cell density. Thus, the best architecture for a particular problem depends on the number of computing cells required. The results also show that with further research, next-generation FPGAs can be expected to accelerate single-processor computations as much as 22,000 times.

Browsing by Author "Jones, Mark T."

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