Browsing by Author "Karthikeyan, Sengunthar"
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- Design Considerations and Quantum Confinement Effect in Monolithic ϵ-Ge/InxGa1-xAs Nanoscale FinFETs Down to N5 NodeJoshi, Rutwik; Karthikeyan, Sengunthar; Hudait, Mantu K. (IEEE, 2022-12-01)In this work, we have studied the effect of material parameters (indium (In) composition and doping), geometrical parameters (channel length L, fin width W, aspect ratio AR), and quantum confinement (QC) on the performance and operability of a ε-Ge/InxGa1-xAs hybrid CMOS system. In this system, the In compositional InxGa1-xAs and tensile strained Ge (ε-Ge) grown on the InxGa1-xAs layer, were used as n- and p-channel FinFETs, respectively. The In composition in InxGa1-xAs layer (lattice matched with graded InxAl1-xAs buffer) determines the amount of tensile strain in Ge. This hybrid system utilizes the benefits of metamorphic (InxGa1-xAs/InxAl1-xAs) as well as pseudomorphic (ε- Ge/InxGa1-xAs) heteroepitaxy to create high performance tunable complementary devices, suitable for 0.5 V CMOS operation. The device metrics such as, threshold voltage, on-current (ION), offcurrent (IOFF), subthreshold-swing (SS), and drain induced barrier lowering (DIBL), and their dependence on material and geometrical parameters were evaluated using self-consistent analytical solvers scaled down to the N5 node. At these scaled dimensions, this hybrid system demonstrated ultra-low leakage current and SS for the n-FinFET and p-FinFET of 10 pA/μm, 27 nA/μm, 85 mV/dec and 95 mV/dec, respectively. With the effect of QC, we identify a transition fin width (WT) associated with scaling of alternate channel FinFETs, at which the performance is optimum and below WT, the benefits of scaling are diminished. Moreover, this hybrid system has a potential to find applications in optoelectronic and RF systems as well as high-performance computing.
- Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAsJoshi, Rutwik; Karthikeyan, Sengunthar; Hudait, Mantu K. (IEEE, 2023)In this work, we have analyzed novel p-channel nanosheet-FET (NSFET) architectures, which utilize Ge channel grown heteroepitaxially on GaAs with an intermediate AlAs etchstop/ buffer layer. The lattice matched Ge/AlAs heterostructure offers significant benefits for gate all-around (GAA) CMOS devices such as: (i) defect-free interface and channel, (ii) ease of fabrication owing to ~ 105:1 etch selectivity between AlAs and Ge, (iii) well-established and transferrable material growth and process, (iv) superior performance and low-power dissipation, (v) no limitation of sheet thickness, and (vi) higher number of vertically stacked sheets. The transition from the well-established FinFET architecture to the Ge p-NSFET will improve ION by 12% to 0.11 mA/μm, SS by 9% to 86 mV/dec and ION/IOFF ratio by ~ 5×, at the N5 node. In addition, the use of InxGa1-xAs strain template to sustain a tunable tensile strain in Ge through pseudomorphic growth, can result in an additional 40% improvement in ION and 8% in SS, at a strain of 1% for the p-NSFET. Leveraging the lattice matched Ge/AlAs growth, the 3D stacking of a large number of nanosheets is possible, and a significant boost in ION (~ 4×) is obtained with 8 layers despite of parasitics induced selfloading. In applications requiring high drive current, increasing the number of stacked Ge nanosheets is the most efficient design pathway to improve circuit delay and area-delay-product. This system shows suitability for low-power and high-performance applications for dimensions down to N0.7, where the ION is ~ 0.6mA/μm and the SS is 81 mV/dec.
- High carrier lifetimes in epitaxial germanium-tin/Al(In)As heterostructures with variable tin compositionHudait, Mantu K.; Johnston, Steven W.; Clavel, Michael B.; Bhattacharya, Shuvodip; Karthikeyan, Sengunthar; Joshi, Rutwik (Royal Society of Chemistry, 2022-06-23)Group IV-based germanium-tin (Ge1−ySny) compositional materials have recently shown great promise for infrared detection, light emission and ultra-low power transistors. High carrier lifetimes are desirable for enhancing the detection limit and efficiency of photodetectors, low threshold current density in lasers, and low tunneling barrier height by lowering defects and dislocations at the heterointerface of a source and a channel. Here, carrier lifetimes in epitaxial germanium (Ge) and variable tin (Sn) compositional Ge1−ySny materials were experimentally determined on GaAs substrates using the contactless microwave photoconductive decay (μ-PCD) technique at an excitation wavelength of 1500 nm. Sharp (2 × 2) reflection high energy electron diffraction patterns and low surface roughness were observed from the surface of the Ge0.97Sn0.03 epilayer. X-ray rocking curves from Ge0.97Sn0.03 and Ge0.94Sn0.06 layers demonstrated the pseudomorphic and lattice-matched growth on AlAs and In0.12Al0.88As buffers, respectively, further substantiated by reciprocal space maps and abrupt heterointerfaces evident from the presence of Pendellösung oscillations. High effective carrier lifetimes of 150 ns to 450 ns were measured for Ge1−ySny epilayers as a function of Sn composition, surface roughness, growth temperature, and layer thickness. The observed increase in the carrier lifetime with an increasing Ge layer thickness and a reducing surface roughness, by incorporating Sn, were explained. The enhancement of the carrier lifetime with an increasing Sn concentration was achieved by controlling the defects with lattice-matched Ge0.94Sn0.06/In0.12Al0.88As heterointerfaces or the pseudomorphic growth of Ge0.94Sn0.06 on GaAs. Therefore, our monolithic integration of variable Sn alloy compositional Ge1−ySny materials with high carrier lifetimes opens avenues to realize electronic and optoelectronic devices.
- Monolithically Cointegrated Tensile Strained Germanium and InxGa1−xAs FinFETs for Tunable CMOS LogicJoshi, Rutwik; Karthikeyan, Sengunthar; Hudait, Mantu K. (IEEE, 2022-08-01)In this article, we have evaluated the merits of monolithically cointegrated alternate channel complementary metal-oxide-semiconductor (CMOS) device architecture, utilizing tensile strained germanium (ε-Ge) for the p-channel FinFET and variable indium (In) compositional InxGa1−xAs (0.10 ≤ x ≤ 0.53) for the n-channel FinFET. The device simulation models were calibrated using the experimental results of Ge and InGaAs FinFETs and subsequently transferred to the cointegrated Ge and InxGa1−x As structure while keeping the device simulation parameters fixed. The device parameters, such as VT, Ion, Ioff, and subthreshold-swing (SS), were determined for identical fin dimensions for n- and p-channel FinFETs as a function of In composition that alters the tensile strain in Ge. These parameters are controllable during the heteroepitaxial growth by varying In composition in InxGa1−xAs. ε-Ge p-FinFET is shown to be superior in terms of SS and Ion/Ioff ratio compared with other competing architectures. The cointegrated architecture of CMOS inverter exhibited an optimum performance over a range of In compositions from 20% to 40% while driving fan-out fan-out 1 (FO-1) and FO-4 load configurations. In addition, the CMOS inverter with symmetric rise and fall times as well as noise-immune functionality demonstrated 150 GHz of operating frequency with 30-nW total power dissipation at 20% In composition, and hence a superior power-delay-product comparable with International Technology Roadmap for Semiconductors (ITRS) standards. Moreover, the three-stage CMOS ring oscillator performance was evaluated with various In compositions to be stable and power efficient. Thus, the cointegrated approach has a potential to: 1) simplify large-scale CMOS integration and 2) be compatible with optoelectronic materials.