Browsing by Author "Li, Huaicheng"
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- Design Tradeoffs in CXL-Based Memory Pools for Public Cloud PlatformsBerger, Daniel S.; Ernst, Dan; Li, Huaicheng; Zardoshti, Pantea; Shah, Monish; Rajadnya, Samir; Lee, Scott; Hsu, Lisa; Agarwal, Ishwar; Hill, Mark D.; Bianchini, Ricardo (IEEE, 2023-02)DRAM is a key driver of performance and cost in public cloud servers. At the same time, a significant amount of DRAM is underutilized due to fragmented use across servers. Emerging interconnects such as CXL offer a path towards improving utilization through memory pooling. However, the design space of CXL-based memory systems is large, with key questions around the size, reach, and topology of the memory pool. At the same time, using pools requires navigating complex design constraints around performance, virtualization, and management. This paper discusses why cloud providers should deploy CXL memory pools, key design constraints, and observations in designing towards practical deployment. We identify configuration examples with significant positive return of investment.
- Disaggregated Zoned Namespace for Multi-tenancy ScenariosRamakrishnapuram Selvanathan, Subhalakshmi (Virginia Tech, 2024-05-22)The traditional block-based interface used in flash-based Solid State Drives (SSDs) imposes limitations on performance and endurance due to write amplification and garbage collection overheads. In response to these challenges, the NVMe Zoned Namespaces (ZNS) devices introduces a novel storage interface organized into zones, optimizing garbage collection and reducing write amplification. This research delves into the exploration and profiling of ZNS device characteristics, aiming to enhance user comprehension and utilization. Additionally, the study investigates the integration of ZNS devices into disaggregated storage frameworks to improve resource utilization, proposing server-side management features to simplify client operations and minimize overhead. By offering insights for future development and optimization of ZNS-based storage solutions, this work contributes to advancing storage technology and addressing the shortcomings of traditional block-based interfaces. Through extensive experimentation and analysis, this study sheds light on the optimal configurations and deployment strategies for ZNS-based storage solutions.
- Extending and Programming the NVMe I/O Determinism Interface for Flash ArraysLi, Huaicheng; Putra, Martin; Shi, Ronald; Kurnia, Fadhil; Lin, Xing; Do, Jaeyoung; Kistijantoro, Achmad; Ganger, Gregory; Gunawi, Haryadi (ACM, 2023-01-11)Predictable latency on flash storage is a long-pursuit goal, yet unpredictability stays due to the unavoidable disturbance from many well-known SSD internal activities. To combat this issue, the recent NVMe IO Determinism (IOD) interface advocates host-level controls to SSD internal management tasks. Although promising, challenges remain on how to exploit it for truly predictable performance. We present IODA,1 an I/O deterministic flash array design built on top of small but powerful extensions to the IOD interface for easy deployment. IODA exploits data redundancy in the context of IOD for a strong latency predictability contract. In IODA, SSDs are expected to quickly fail an I/O on purpose to allow predictable I/Os through proactive data reconstruction. In the case of concurrent internal operations, IODA introduces busy remaining time exposure and predictable-latency-window formulation to guarantee predictable data reconstructions. Overall, IODA only adds five new fields to the NVMe interface and a small modification in the flash firmware while keeping most of the complexity in the host OS. Our evaluation shows that IODA improves the 95–99.99th latencies by up to 75×. IODA is also the nearest to the ideal, no disturbance case compared to seven state-of-the-art preemption, suspension, GC coordination, partitioning, tiny-tail flash controller, prediction, and proactive approaches.