Browsing by Author "Liu, Pei-Hsin"
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- Advanced Control Schemes for High-Bandwidth Multiphase Voltage RegulatorsLiu, Pei-Hsin (Virginia Tech, 2015-05-13)Advances in transistor-integration technology and multi-core technology of the latest microprocessors have driven transient requirements to become more and more stringent. Rather than relying on the bulky output capacitors as energy-storage devices, increasing the control bandwidth (BW) of the multiphase voltage regulator (VR) is a more cost-effective and space-saving approach. However, it is found that the stability margin of current-mode control in high-BW design is very sensitive to operating conditions and component tolerance, depending on the performance of the current-sensing techniques, modulation schemes, and interleaving approaches. The primary objective of this dissertation is to investigate an advanced multiphase current-mode control, which provides accurate current sensing, enhances the stability margin in high-BW design, and adaptively compensates the parameter variations. Firstly, an equivalent circuit model for generic current-mode controls using DCR current sensing is developed to analyze the impact of component tolerance in high-BW design. Then, the existing state-of-the-art auto-tuning method used to improve current-sensing accuracy is reviewed, and the deficiency of using this method in a multiphase VR is identified. After that, enlightened by the proposed model, a novel auto-tuning method is proposed. This novel method features better tuning performance, noise-insensitivity, and simpler implementation than the state-of-the-art method. Secondly, the current state-of-the-art adaptive current-mode control based on constant-frequency PWM is reviewed, and its inability to maintain adequate stability margin in high-BW design is recognized. Therefore, a new external ramp compensation technique is proposed to keep the stability margin insensitive to the operating conditions and component tolerance, so the proposed high-BW constant-frequency control can meet the transient requirement without the presence of bulky output capacitors. The control scheme is generic and can be used in various kinds of constant-frequency controls, such as peak-current-mode, valley-current-mode, and average-current-mode configurations. Thirdly, an interleaving technique incorporating an adaptive PLL loop is presented, which enables the variable-frequency control to push the BW higher than proposed constant-frequency control, and avoids the beat-frequency input ripple. A generic small-signal model of the PLL loop is derived to investigate the stability issue caused by the parameter variations. Then, based on the proposed model, a simple adaptive control is developed to allow the BW of the PLL loop to be anchored at the highest phase margin. The adaptive PLL structure is applicable to different types of variable-frequency control, including constant on-time control and ramp pulse modulation. Fourthly, a hybrid interleaving structure is explored to simplify the implementation of the adaptive PLL structure in an application with more phases. It combines the adaptive PLL loop with a pulse-distribution technique to take the advantage of the high-BW design and fast transient response without adding a burden to the controller implementation. As a conclusion, based on the proposed analytical models, effective control concepts, systematic optimization strategies, viable implementations are fully investigated for high-BW current-mode control using different modulation techniques. Moreover, all the modeling results and the system performance are verified through simulation with a practical output filter model and an advanced mixed-signal experimental platform based on the latest MHz VR design on the laptop motherboard. In consequence, the multiphase VRs in future computation systems can be scalable easier with proposed multiphase configurations, increase the system reliability with proposed adaptive loop compensation, and minimize the total system footprint of the VR with the superior transient performance.
- Current mode control DC-DC converter with single step load transient response(United States Patent and Trademark Office, 2019-06-04)A power converter using constant on-time (COT) or ramp pulse modulation (RPM) control achieves more rapid resumption of steady-state operation after a step-up load transient by extending an on-time of a switching pulse by interrupting a ramp voltage waveform that is compared with a threshold that equals a threshold voltage at the termination of a switching pulse or increasing a voltage with which the ramp voltage is compared. These techniques are applied to both single-phase and multi-phase power converters.
- External ramp autotuning for current mode control of switching converter(United States Patent and Trademark Office, 2017-06-13)Peak current, valley current or average current mode controlled power converters in either digital or analog implementations obtain a stabilized feedback loop and allow high system bandwidth design by use of an external ramp generator using a slope computation equation or design parameters based on fixing the quality factor of a double pole at one-half of the switching frequency at a desired value The slope of the external ramp waveform is tuned automatically with knowledge of the slope change in the waveform of inductor current of a power converter derived by differentiating a waveform in the current feedback loop. This autotuning of the external ramp generator provides immunity of quality factor change under variations of duty cycle, component values of topological change of the power converter.
- Hybrid interleaving structure with adaptive phase locked loop for variable frequency controlled switching converter(United States Patent and Trademark Office, 2018-07-03)In a multi-phase power converter using a phase-locked loop (PLL) arrangement for interleaving of pulse frequency modulated (PFM) pulses of the respective phases, improved transient response, improved stability of high bandwidth output voltage feedback loop, guaranteed stability of the PLL loop and avoidance of jittering and phase cancellation issues are achieved by anchoring the bandwidth at the frequency of peak phase margin. This methodology is applicable to multi-phase power conveners of any number of phases and any known or foreseeable topology for individual phases and is not only applicable to power converters operating under constant on-time control, but is extendable to ramp pulse modulation (RPM) control and hysteresis control. Interleaving of pulses from all phases is simplified through use of phase managers with a reduced number of PLLS using hybrid interleaving arrangements that do not exhibit jittering even when ripple is completely canceled.
- Transient performance improvement for constant on-time power converters(United States Patent and Trademark Office, 2018-10-23)Response of a variable frequency switching constant on-time or adaptive on-time controlled power converter to a large step-up or step-down change in load is improved with a simple circuit that detects magnitude and polarity of a change in output voltage and initiates, extends or terminates conduction of power pulses from an input source through said power converter. Both the amplitude and duration of undershoot or overshoot of the transient response are reduced or, alternatively, the capacitance of an output filter may be significantly reduced and still provide comparable transient performance. The fast adaptive on-time control is applicable to multi-phase power converters using phase managers or one or more phase-locked loops for interleaving of power pulses.
- V^2 power converter control with capacitor current ramp compensation(United States Patent and Trademark Office, 2017-03-21)Operation of a switching power converter having an output capacitor having a small equivalent series resistance (ESR) is stabilized and jitter reduced by sensing capacitor current with gain and combining the resulting signal with the output voltage signal to provide a feedback signal to control switching of the power converter. capacitor current can be sensed without interfering with operation of the filter capacitor by providing a branch circuit having a time constant matched to the output or filter capacitor but an arbitrarily high impedance so as to be effectively lossless. The gain provided in the capacitor current signal can be tuned to provide optimally short settling time after load transients; generally within one switching cycle. Matching of time constants and/or tuning of gain can be performed automatically.