VTechWorks Repository :: Browsing by Author "Martin, Thomas L."

Browsing by Author "Martin, Thomas L."

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Activity Recognition Processing in a Self-Contained Wearable System
Chong, Justin Brandon (Virginia Tech, 2008-09-12)
Electronic textiles provide an effective platform to contain wearable computing elements, especially components geared towards the application of activity recognition. An activity recogni tion system built into a wearable textile substrate can be utilized in a variety of areas including health monitoring, military applications, entertainment, and fashion. Many of the activity recognition and motion capture systems previously developed have several drawbacks and limitations with regard to their respective designs and implementations. Some such systems are often times expensive, not conducive to mass production, and may be difficult to calibrate. An effective system must also be scalable and should be deployable in a variety of environments and contexts. This thesis presents the design and implementation of a self-contained motion sensing wearable electronic textile system with an emphasis toward the application of activity recognition. The system is developed with scalability and deployability in mind, and as such, utilizes a two-tier hierarchical model combined with a network infrastructure and wireless connectivity. An example prototype system, in the form of a jumpsuit garment, is presented and is constructed from relatively inexpensive components and materials.
Activity Recognition using Singular Value Decomposition
Jolly, Vineet Kumar (Virginia Tech, 2006-08-08)
A wearable device that accurately records a user's daily activities is of substantial value. It can be used to enhance medical monitoring by maintaining a diary that lists what a person was doing and for how long. The design of a wearable system to record context such as activity recognition is influenced by a combination of variables. A flexible yet systematic approach for building a software classification environment according to a set of variables is described. The integral part of the software design is the use of a unique robust classifier that uses principal component analysis (PCA) through singular value decomposition (SVD) to perform real-time activity recognition. The thesis describes the different facets of the SVD-based approach and how the classifier inputs can be modified to better differentiate between activities. This thesis presents the design and implementation of a classification environment used to perform activity detection for a wearable e-textile system.
Affective Feedback in a Virtual Reality based Intelligent Supermarket
Saha, Deba Pratim; Martin, Thomas L.; Knapp, R. Benjamin (ACM, 2017)
The probabilistic nature of the inferences in a context-aware intelligent environment (CAIE) renders them vulnerable to erroneous decisions resulting in wrong services. Learning to recognize a user’s negative reactions to such wrong services will enable a CAIE to anticipate a service’s appropriateness. We propose a framework for continuous measurement of physiology to infer a user’s negative-emotions arising from receiving wrong services, thereby implementing an implicit-feedback loop in the CAIE system. To induce such negative-emotions, in this paper, we present a virtualreality (VR) based experimental platform while collecting real-time physiological data from ambulatory wearable sensors. Results from the electrodermal activity (EDA) data analysis reveal patterns that correlate with known features of negative-emotions, indicating the possibility to infer service appropriateness from user’s reactions to a service, thereby closing an implicit-feedback loop for the CAIE.
AlcoZone: An Adaptive Hypermedia based Personalized Alcohol Education
Bhosale, Devdutta (Virginia Tech, 2006-05-08)
In our knowledge based economy, demand for better and effective learning has led to innovative instructional technologies. However, the one-size-fit-all approach taken by many e-Learning systems is not adequate to the different requirements of people who have different goals, preferences, and previous knowledge about a subject. Many e-Learning systems have approached this problem with personalized and customized content. However, many of these systems are closely tied to one particular subject that they are trying to teach; authoring of courses on different subjects using the same framework is a difficult process. Adaptive Hypermedia is an approach in which content presentation and navigation assistance is personalized depending on the requirements of the user. The user requirements are represented using a user model, while the content is represented using a content model. By using a set of algorithms, an Adaptive Hypermedia based system is able to select the most appropriate content to be presented, as the user interacts with the system. The objective of AlcoZone is to educate all of the 5,000 freshman students of Virginia Tech about alcohol education using Adaptive Hypermedia technology, as part of the mandatory university requirement. The course presents different content to different students based on their drinking pattern. AlcoZone integrates Curriculum Sequencing, Multimedia and Interactivity, Alternate Content Explanation, and Navigational Assistance to make the course interesting for students. This research investigates the design & implementation of AlcoZone and its Adaptive Hypermedia based reusable framework for course creation and delivery.
Ambulatory Fall Event Detection with Integrative Ambulatory Measurement (IAM) Framework
Liu, Jian (Virginia Tech, 2008-08-29)
Injuries associated with fall accidents pose a significant health problem to society, both in terms of human suffering and economic losses. Existing fall intervention approaches are facing various limitations. This dissertation presented an effort to advance indirect type of injury prevention approach. The overall objective was to develop a new fall event detection algorithm and a new integrative ambulatory measurement (IAM) framework which could further improve the fall detection algorithm's performance in detecting slip-induced backward falls. This type of fall was chosen because slipping contributes to a major portion of fall-related injuries. The new fall detection algorithm was designed to utilize trunk angular kinematics information as measured by Inertial Measurement Units (IMU). Two empirical studies were conducted to demonstrate the utility of the new detection algorithm and the IAM framework in fall event detection. The first study involved a biomechanical analysis of trunk motion features during common Activities of Daily Living (ADLs) and slip-induced falls using an optical motion analysis system. The second study involved collecting laboratory data of common ADLs and slip-induced falls using ambulatory sensors, and evaluating the performance of the new algorithm in fall event detection. Results from the current study indicated that the backward falls were characterized by the unique, simultaneous occurrence of an extremely high trunk extension angular velocity and a slight trunk extension angle. The quadratic form of the two-dimensional discrimination function showed a close-to-ideal overall detection performance (AUC of ROCa = 0.9952). The sensitivity, specificity, and the average response time associated with the specific configuration of the new algorithm were found to be 100%, 95.65%, and 255ms, respectively. The individual calibration significantly improved the response time by 2.4% (6ms). Therefore, it was concluded that slip-induced backward fall was clearly distinguishable from ADLs in the trunk angular phase plot. The new algorithm utilizing a gyroscope and orientation sensor was able to detect backward falls prior to the impact, with a high level of sensitivity and specificity. In addition, individual calibration provided by the IAM framework was able to further enhance the fall detection performance.
An Ambulatory Monitoring Algorithm to Unify Diverse E-Textile Garments
Blake, Madison Thomas (Virginia Tech, 2014-03-11)
In this thesis, an activity classification algorithm is developed to support a human ambulatory monitoring system. This algorithm, to be deployed on an e-textile garment, represents the enabling step in creating a wide range of garments that can use the same classifier without having to re-train for different sensor types. This flexible operation is made possible by basing the classifier on an abstract model of the human body that is the same across all sensor types and subject bodies. In order to support low power devices inherent for wearable systems, the algorithm utilizes regular expressions along with a tree search during classification. To validate the approach, a user study was conducted using video motion capture to record subjects performing a variety of activities. The subjects were randomly placed into two groups, one used to generate the activities known by the classifier and another to be used as observation to the classifier. These two sets were used to gain insight on the performance of the algorithm. The results of the study demonstrate that the algorithm can successfully classify observations, so as long as precautions are taken to prevent the activities known by the classifier to become too large. It is also shown that the tree search performed by the classification can be utilized to partially classify observations that would otherwise be rejected by the classifier. The user study additionally included subjects that performed activities purely used for observations to the classifier. With this set of recordings, it was demonstrated that the classifier does not over-fit and is capable of halting the classification of an observation.
Analysis of a self-contained motion capture garment for e-textiles
Lewis, Robert Alan (Virginia Tech, 2011-05-04)
Wearable computers and e-textiles are becoming increasingly widespread in today's society. Motion capture is one of the many potential applications for on-body electronic systems. Previous work has been performed at Virginia Tech's E-textiles Laboratory to design a framework for a self-contained loose fit motion capture system. This system gathers information from sensors distributed throughout the body on a "smart" garment. This thesis presents the hardware and software components of the framework, along with improvements made to it. This thesis also presents an analysis of both the on-body and off-body network communication to determine how many sensors can be supported on the garment at a given time. Finally, this thesis presents a method for determining the accuracy of the smart garment and shows how it compares against a commercially available motion capture system.
An Application Framework for a Power-Aware Processor Architecture
Mandlekar, Anup Shrikant (Virginia Tech, 2012-08-07)
The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency, was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software applications to test the architecture performance. The application framework is integrated with the prior automation framework bringing software applications at the right level of abstraction. The processor architecture design is made flexible and scalable, making it suitable for a wide range of applications. Additionally, an embedded flash memory based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory.
Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware
Farag, Mohammed Morsy Naeem (Virginia Tech, 2012-09-17)
Embedded electronics are widely employed in cyber-physical systems (CPSes), which tightly integrate and coordinate computational and physical elements. CPSes are extensively deployed in security-critical applications and nationwide infrastructure. Perimeter security approaches to preventing malware infiltration of CPSes are challenged by the complexity of modern embedded systems incorporating numerous heterogeneous and updatable components. Global supply chains and third-party hardware components, tools, and software limit the reach of design verification techniques and introduce security concerns about deliberate Trojan inclusions. As a consequence, skilled attacks against CPSes have demonstrated that these systems can be surreptitiously compromised. Existing run-time security approaches are not adequate to counter such threats because of either the impact on performance and cost, lack of scalability and generality, trust needed in global third parties, or significant changes required to the design flow. We present a protection scheme called Run-time Enhancement of Trusted Computing (RETC) to enhance trust in CPSes containing untrusted software and hardware. RETC is complementary to design-time verification approaches and serves as a last line of defense against the rising number of inexorable threats against CPSes. We target systems built using reconfigurable hardware to meet the flexibility and high-performance requirements of modern security protections. Security policies are derived from the system physical characteristics and component operational specifications and translated into synthesizable hardware integrated into specific interfaces on a per-module or per-function basis. The policy-based approach addresses many security challenges by decoupling policies from system-specific implementations and optimizations, and minimizes changes required to the design flow. Interface guards enable in-line monitoring and enforcement of critical system computations at run-time. Trust is only required in a small set of simple, self-contained, and verifiable guard components. Hardware trust anchors simultaneously addresses the performance, flexibility, developer productivity, and security requirements of contemporary CPSes. We apply RETC to several CPSes having common security challenges including: secure reconfiguration control in reconfigurable cognitive radio platforms, tolerating hardware Trojan threats in third-party IP cores, and preserving stability in process control systems. High-level architectures demonstrated with prototypes are presented for the selected applications. Implementation results illustrate the RETC efficiency in terms of the performance and overheads of the hardware trust anchors. Testbenches associated with the addressed threat models are generated and experimentally validated on reconfigurable platform to establish the protection scheme efficacy in thwarting the selected threats. This new approach significantly enhances trust in CPSes containing untrusted components without sacrificing cost and performance.
An Architecture for Electronic Textiles
Jones, Mark T.; Martin, Thomas L.; Sawyer, Braden (ICST, 2008)
This paper makes a case for a communication architecture for electronic textiles (e-textiles). The properties and re- quirements of e-textile garments are described and analyzed. Based on these properties, the authors make a case for em- ploying wired, digital communication as the primary on- garment communication network. The implications of this design choice for the hardware architecture for e-textiles are discussed.
Architectures for e-Textiles
Nakad, Zahi Samir (Virginia Tech, 2003-12-10)
The huge advancement in the textiles industry and the accurate control on the mechanization process coupled with cost-effective manufacturing offer an innovative environment for new electronic systems, namely electronic textiles. The abundance of fabrics in our regular life offers immense possibilities for electronic integration both in wearable and large-scale applications. Augmenting this technology with a set of precepts and a simulation environment creates a new software/hardware architecture with widely useful implementations in wearable and large-area computational systems. The software environment acts as a functional modeling and testing platform, providing estimates of design metrics such as power consumption. The construction of an electronic textile (e-textile) hardware prototype, a large-scale acoustic beamformer, provides a basis for the simulator and offers experience in building these systems. The contributions of this research focus on defining the electronic textile architecture, creating a simulation environment, defining a networking scheme, and implementing hardware prototypes.
ATPG and DFT Algorithms for Delay Fault Testing
Liu, Xiao (Virginia Tech, 2004-06-10)
With ever shrinking geometries, growing metal density and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are usually unacceptable for large scale designs due to the prohibitive cost of functional test patterns and the difficulty in achieving very high fault coverage. Scan-based delay testing, which could ensure a high delay fault coverage at reasonable development cost, provides a good alternative to the at-speed functional test. This dissertation addresses several key challenges in scan-based delay testing and develops efficient Automatic Test Pattern Generation (ATPG) and Design-for-testability (DFT) algorithms for delay testing. In the dissertation, two algorithms are first proposed for computing and applying transition test patterns using stuck-at test vectors, thus avoiding the need for a transition fault test generator. The experimental results show that we can improve both test data volume and test application time by 46.5% over a commercial transition ATPG tool. Secondly, we propose a hybrid scan-based delay testing technique for compact and high fault coverage test set, which combines the advantages of both the skewed-load and broadside test application methods. On an average, about 4.5% improvement in fault coverage is obtained by the hybrid approach over the broad-side approach, with very little hardware overhead. Thirdly, we propose and develop a constrained ATPG algorithm for scan-based delay testing, which addresses the overtesting problem due to the possible detection of functionally untestable faults in scan-based testing. The experimental results show that our method efficiently generates a test set for functionally testable transition faults and reduces the yield loss due to overtesting of functionally untestable transition faults. Finally, a new approach on identifying functionally untestable transition faults in non-scan sequential circuits is presented. We formulate a new dominance relationship for transition faults and use it to help identify more untestable transition faults on top of a fault-independent method based on static implications. The experimental results for ISCAS89 sequential benchmark circuits show that our approach can identify many more functionally untestable transition faults than previously reported.
Automatic Generation of Test Cases for Agile using Natural Language Processing
Rane, Prerana Pradeepkumar (Virginia Tech, 2017-03-24)
Test case design and generation is a tedious manual process that requires 40-70% of the software test life cycle. The test cases written manually by inexperienced testers may not offer a complete coverage of the requirements. Frequent changes in requirements reduce the reusability of the manually written test cases costing more time and effort. Most projects in the industry follow a Behavior-Driven software development approach to capturing requirements from the business stakeholders through user stories written in natural language. Instead of writing test cases manually, this thesis investigates a practical solution for automatically generating test cases within an Agile software development workflow using natural language-based user stories and acceptance criteria. However, the information provided by the user story is insufficient to create test cases using natural language processing (NLP), so we have introduced two new input parameters, Test Scenario Description and Dictionary, to improve the test case generation process. To establish the feasibility, we developed a tool that uses NLP techniques to generate functional test cases from the free-form test scenario description automatically. The tool reduces the effort required to create the test cases while improving the test coverage and quality of the test suite. Results from the feasibility study are presented in this thesis.
Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs
Subbarayan, Guruprasad (Virginia Tech, 2010-11-19)
FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed has resulted in longer runtimes of the implementation tools. We address the implementation problem using a divide-and-conquer approach in which some device area and circuit speed is sacrificed for improved implementation turnaround time. The PATIS floorplanner enables dynamic modular design that accelerates implementation for incremental changes to a design. While the existing implementation flows facilitate timing closure late in the design cycle by reusing the layout of unmodified blocks, dynamic modular design accelerates implementation by achieving timing closure for each block independently. A complete re-implementation is still rapid as the design blocks can be processed by independent and concurrent invocations of the standard tools. PATIS creates the floorplan for implementing modules in the design. Bus macros serve as module interfaces and enable independent implementation of the modules. The dynamic modular design flow achieves around 10x speedup over the standard design flow for our benchmark designs.
Automatically Locating Sensor Position on an E-textile Garment Via Pattern Recognition
Love, Andrew R. (Virginia Tech, 2009-09-30)
Electronic textiles are a sound platform for wearable computing. Many applications have been devised that use sensors placed on these textiles for fields such as medical monitoring and military use or for display purposes. Most of these applications require that the sensors have known locations for accurate results. Activity recognition is one application that is highly dependent on knowledge of the sensor position. Therefore, this thesis presents the design and implementation of a method whereby the location of the sensors on the electronic textile garments can be automatically identified when the user is performing an appropriate activity. The software design incorporates principle component analysis using singular value decomposition to identify the location of the sensors. This thesis presents a method to overcome the problem of bilateral symmetry through sensor connector design and sensor orientation detection. The scalability of the solution is maintained through the use of culling techniques. This thesis presents a flexible solution that allows for the fine-tuning of the accuracy of the results versus the number of valid queries, depending on the constraints of the application. The resulting algorithm is successfully tested on both motion capture and sensor data from an electronic textile garment.
Biologically Inspired Cognitive Radio Engine Model Utilizing Distributed Genetic Algorithms for Secure and Robust Wireless Communications and Networking
Rieser, Christian James (Virginia Tech, 2004-09-29)
This research focuses on developing a cognitive radio that could operate reliably in unforeseen communications environments like those faced by the disaster and emergency response communities. Cognitive radios may also offer the potential to open up secondary or complimentary spectrum markets, effectively easing the perceived spectrum crunch while providing new competitive wireless services to the consumer. A structure and process for embedding cognition in a radio is presented, including discussion of how the mechanism was derived from the human learning process and mapped to a mathematical formalism called the BioCR. Results from the implementation and testing of the model in a hardware test bed and simulation test bench are presented, with a focus on rapidly deployable disaster communications. Research contributions include developing a biologically inspired model of cognition in a radio architecture, proposing that genetic algorithm operations could be used to realize this model, developing an algorithmic framework to realize the cognition mechanism, developing a cognitive radio simulation toolset for evaluating the behavior the cognitive engine, and using this toolset to analyze the cognitive engineÃ Âs performance in different operational scenarios. Specifically, this research proposes and details how the chaotic meta-knowledge search, optimization, and machine learning properties of distributed genetic algorithm operations could be used to map this model to a computable mathematical framework in conjunction with dynamic multi-stage distributed memories. The system formalism is contrasted with existing cognitive radio approaches, including traditionally brittle artificial intelligence approaches. The cognitive engine architecture and algorithmic framework is developed and introduced, including the Wireless Channel Genetic Algorithm (WCGA), Wireless System Genetic Algorithm (WSGA), and Cognitive System Monitor (CSM). Experimental results show that the cognitive engine finds the best tradeoff between a host radio's operational parameters in changing wireless conditions, while the baseline adaptive controller only increases or decreases its data rate based on a threshold, often wasting usable bandwidth or excess power when it is not needed due its inability to learn. Limitations of this approach include some situations where the engine did not respond properly due to sensitivity in algorithm parameters, exhibiting ghosting of answers, bouncing back and forth between solutions. Future research could be pursued to probe the limits of the engineÃ Âs operation and investigate opportunities for improvement, including how best to configure the genetic algorithms and engine mathematics to avoid engine solution errors. Future research also could include extending the cognitive engine to a cognitive radio network and investigating implications for secure communications.
BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs
Morford, Casey Justin (Virginia Tech, 2005-12-15)
With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow.
Capacity Metric for Chip Heterogeneous Multiprocessors
Otoom, Mwaffaq Naif (Virginia Tech, 2012-02-23)
The primary contribution of this thesis is the development of a new performance metric, Capacity, which evaluates the performance of Chip Heterogeneous Multiprocessors (CHMs) that process multiple heterogeneous channels. Performance metrics are required in order to evaluate any system, including computer systems. A lack of appropriate metrics can lead to ambiguous or incorrect results, something discovered while developing the secondary contribution of this thesis, that of workload modes for CHMs — or Workload Specific Processors (WSPs). For many decades, computer architects and designers have focused on techniques that reduce latency and increase throughput. The change in modern computer systems built around CHMs that process multi-channel communications in the service of single users calls this focus into question. Modern computer systems are expected to integrate tens to hundreds of processor cores onto single chips, often used in the service of single users, potentially as a way to access the Internet. Here, the design goal is to integrate as much functionality as possible during a given time window. Without the ability to correctly identify optimal designs, not only will the best performing designs not be found, but resources will be wasted and there will be a lack of insight to what leads to better performing designs. To address performance evaluation challenges of the next generation of computer systems, such as multicore computers inside of cell phones, we found that a structurally different metric is needed and proceeded to develop such a metric. In contrast to single-valued metrics, Capacity is a surface with dimensionality related to the number of input streams, or channels, processed by the CHM. We develop some fundamental Capacity curves in two dimensions and show how Capacity shapes reveal interaction of not only programs and data, but the interaction of multiple data streams as they compete for access to resources on a CHM as well. For the analysis of Capacity surface shapes, we propose the development of a demand characterization method in which its output is in the form of a surface. By overlaying demand surfaces over Capacity surfaces, we are able to identify when a system meets its demands and by how much. Using the Capacity metric, computer performance optimization is evaluated against workloads in the service of individual users instead of individual applications, aggregate applications, or parallel applications. Because throughput was originally derived by drawing analogies between processor design and pipelines in the automobile industry, we introduce our Capacity metric for CHMs by drawing an analogy to automobile production, signifying that Capacity is the successor to throughput. By developing our Capacity metric, we illustrate how and why different processor organizations cannot be understood as being better performers without both magnitude and shape analysis in contrast to other metrics, such as throughput, that consider only magnitude. In this work, we make the following major contributions: • Definition and development of the Capacity metric as a surface with dimensionality related to the number of input streams, or channels, processed by the CHM. • Techniques for analysis of the Capacity metric. Since the Capacity metric was developed out of necessity, while pursuing the development of WSPs, this work also makes the following minor contributions: • Definition and development of three foundations in order to establish an experimental foundation — a CHM model, a multimedia cell phone example, and a Workload Specific Processor (WSP). • Definition of Workload Modes, which was the original objective of this thesis. • Definition and comparison of two approaches to workload mode identification at run time; The Workload Classification Model (WCM) and another model that is based on Hidden Markov Models (HMMs). • Development of a foundation for analysis of the Capacity metric, so that the impact of architectural features in a CHM may be better understood. In order to do this, we develop a Demand Characterization Method (DCM) that characterizes the demand of a specific usage pattern in the form of a curve (or a surface in general). By doing this, we will be able to overlay demand curves over Capacity curves of different architectures to compare their performance and thus identify optimal performing designs.
Classifier for Activities with Variations
Younes, Rabih; Jones, Mark T.; Martin, Thomas L. (MDPI, 2018-10-18)
Most activity classifiers focus on recognizing application-specific activities that are mostly performed in a scripted manner, where there is very little room for variation within the activity. These classifiers are mainly good at recognizing short scripted activities that are performed in a specific way. In reality, especially when considering daily activities, humans perform complex activities in a variety of ways. In this work, we aim to make activity recognition more practical by proposing a novel approach to recognize complex heterogeneous activities that could be performed in a wide variety of ways. We collect data from 15 subjects performing eight complex activities and test our approach while analyzing it from different aspects. The results show the validity of our approach. They also show how it performs better than the state-of-the-art approaches that tried to recognize the same activities in a more controlled environment.
Communication Synthesis for MIMO Decoder Matrices
Quesenberry, Joshua Daniel (Virginia Tech, 2011-08-09)
The design in this work provides an easy and cost-efficient way of performing an FPGA implementation of a specific algorithm through use of a custom hardware design language and communication synthesis. The framework is designed to optimize performance with matrix-type mathematical operations. The largest matrices used in this process are 4x4 matrices. The primary example modeled in this work is MIMO decoding. Making this possible are 16 functional unit containers within the framework, with generalized interfaces, which can hold custom user hardware and IP cores. This framework, which is controlled by a microsequencer, is centered on a matrix-based memory structure comprised of 64 individual dual-ported memory blocks. The microsequencer uses an instruction word that can control every element of the architecture during a single clock cycle. Routing to and from the memory structure uses an optimized form of a crossbar switch with predefined routing paths supporting any combination of input/output pairs needed by the algorithm. A goal at the start of the design was to achieve a clock speed of over 100 MHz; a clock speed of 183 MHz has been achieved. This design is capable of performing a 4x4 matrix inversion within 335 clock cycles, or 1,829 ns. The power efficiency of the design is measured at 17.15 MFLOPS/W.

Browsing by Author "Martin, Thomas L."

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