Browsing by Author "Philippidis, Cesar"

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    Offloading Datacenter Jobs to RISC-V Hardware for Improved Performance and Power Efficiency
    Heerekar, Balvansh; Philippidis, Cesar; Chuang, Ho-Ren; Olivier, Pierre; Barbalace, Antonio; Ravindran, Binoy (ACM, 2024-09-16)
    The end of Moore’s Law has brought significant changes in the architecture of servers used in data centers, increasingly incorporating new ISAs beyond x86-64 as well as diverse accelerators. Further, single-board computers have become increasingly efficient and can run certain Linux applications at significantly lower equipment and energy costs compared to traditional servers. Past research has demonstrated that offloading applications at runtime from x86-based servers to ARM-based single-board computers can result in increases in throughput and energy efficiency. The RISC-V architecture has recently gained significant commercial interest, and OS-capable single-board computers with RISC-V cores are increasingly available at the commodity scale. In this paper we propose a system that offloads jobs from an x86 server to a RISC-V single-board computer at runtime, with the goals of improving job throughput and energy saved. Towards this, we port the Popcorn Linux multi-ISA toolchain and runtime framework to RISC-V, enabling the live migration of applications between an x86 Xeon server and a SiFive HiFive RISC-V board. We further propose a scheduling policy, Lowest Slowdown First (LSF) that drives the offloading of long-running and stateful datacenter background jobs from the server to the board, to alleviate workload congestion on the server. LSF’s policy relies on monitoring jobs’ performance on the server, predicting the slowdown they would suffer if running on the board, and migrating the jobs with the lowest estimated slowdown. Our evaluation shows that LSF yields up to 20% increase in throughput while also gaining 16% more energy efficiency for compute-intensive workloads.
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    Xar-Trek: Run-time Execution Migration among FPGAs and Heterogeneous-ISA CPUs
    Horta, Edson; Chuang, Ho-Ren; VSathish, Naarayanan Rao; Philippidis, Cesar; Barbalace, Antonio; Olivier, Pierre; Ravindran, Binoy (ACM, 2021-12-06)
    Datacenter servers are increasingly heterogeneous: from x86 host CPUs, to ARM or RISC-V CPUs in NICs/SSDs, to FPGAs. Previous works have demonstrated that migrating application execution at run-time across heterogeneous-ISA CPUs can yield significant performance and energy gains, with relatively little programmer effort. However, FPGAs have often been overlooked in that context: hardware acceleration using FPGAs involves statically implementing select application functions, which prohibits dynamic and transparent migration. We present Xar-Trek, a new compiler and run-time software framework that overcomes this limitation. Xar-Trek compiles an application for several CPU ISAs and select application functions for acceleration on an FPGA, allowing execution migration between heterogeneous-ISA CPUs and FPGAs at run-time. Xar-Trek’s run-time monitors server workloads and migrates application functions to an FPGA or to heterogeneous-ISA CPUs based on a scheduling policy. We develop a heuristic policy that uses application workload profiles to make scheduling decisions. Our evaluations conducted on a system with x86-64 server CPUs, ARM64 server CPUs, and an Alveo accelerator card reveal 88%-1% performance gains over no-migration baselines.