Browsing by Author "Tang, Wei"

Now showing 1 - 3 of 3
  • Thumbnail Image
    ARQUIN : Architectures for Multinode Superconducting Quantum Computers
    Ang, James; Carini, Gabriella; Chen, Yanzhu; Chuang, Isaac; Demarco, Michael; Economou, Sophia E.; Eickbusch, Alec; Faraon, Andrei; Fu, Kai-mei M.; Girvin, Steven; Hatridge, Michael; Houck, Andrew; Hilaire, Paul; Krsulich, Kevin; Li, Ang; Liu, Chenxu; Liu, Yuan; Martonosi, Margaret; Mckay, David; Misewich, Jim; Ritter, Mark; Schoelkopf, Robert; Stein, Samuel; Sussman, Sara; Tang, Hong; Tang, Wei; Tomesh, Teague; Tubman, Norm; Wang, Chen; Wiebe, Nathan; Yao, Yongxin; Yost, Dillon; Zhou, Yiyu (ACM, 2024-09-19)
    Many proposals to scale quantum technology rely on modular or distributed designs wherein individual quantum processors, called nodes, are linked together to form one large multinode quantum computer (MNQC). One scalable method to construct an MNQC is using superconducting quantum systems with optical interconnects. However, internode gates in these systems may be two to three orders of magnitude noisier and slower than local operations. Surmounting the limitations of internode gates will require improvements in entanglement generation, use of entanglement distillation, and optimized software and compilers. Still, it remains unclear what performance is possible with current hardware and what performance algorithms require. In this article, we employ a systems analysis approach to quantify overall MNQC performance in terms of hardware models of internode links, entanglement distillation, and local architecture. We show how to navigate tradeoffs in entanglement generation and distillation in the context of algorithm performance, lay out how compilers and software should balance between local and internode gates, and discuss when noisy quantum internode links have an advantage over purely classical links. We find that a factor of 10–100× better link performance is required and introduce a research roadmap for the co-design of hardware and software towards the realization of early MNQCs. While we focus on superconducting devices with optical interconnects, our approach is general across MNQC implementations.
  • Thumbnail Image
    Average current-mode control and charge control for PWM converters
    Tang, Wei (Virginia Tech, 1994)
    Two control schemes for PWM converters, average current-mode (ACM) control and charge control, are studied in this dissertation. The small-signal models are derived for continuous-conduction mode PWM converters employing these two controls. Sampled-data modeling is applied to the current loop modeling, and the obtained models are accurate up to half the switching frequency. The relationships between current loop instability and converter operating conditions for both controls are found for the first time. The derived models are verified by both time-domain simulations and experiments. The models can be used for both voltage loop and current loop analysis and designs. Comprehensive design guidelines for PWM converters with both controls are also provided. The small-signal characteristics of these two controls are compared with those of peak current-mode control. The applications of ACM control and charge control to power factor correction (PFC) circuits are studied. Charge control is applied to continuous-conduction mode flyback converter to achieve a single-stage PFC. The current loop instability in PFC circuit and its effect on the input EMI filter design are investigated. The trade-off between the current loop stability nlargin and line current distortion is also discussed.
  • Thumbnail Image
    Reconfigurable Hardware-Based Simulation Modeling of Flexible Manufacturing Systems
    Tang, Wei (Virginia Tech, 2005-11-18)
    This dissertation research explores a reconfigurable hardware-based parallel simulation mechanism that can dramatically improve the speed of simulating the operations of flexible manufacturing systems (FMS). Here reconfigurable hardware-based simulation refers to running simulation on a reconfigurable hardware platform, realized by Field Programmable Gate Array (FPGA). The hardware model, also called simulator, is specifically designed for mimicking a small desktop FMS. It is composed of several micro-emulators, which are capable of mimicking operations of equipment in FMS, such as machine centers, transporters, and load/unload stations. To design possible architectures for the simulator, a mapping technology is applied using the physical layout information of an FMS. Under such a mapping method, the simulation model is decomposed into a cluster of micro emulators on the board where each machine center is represented by one micro emulator. To exploit the advantage of massive parallelism, a kind of star network architecture is proposed, with the robot sitting at the center. As a pilot effort, a prototype simulator has been successfully built. A new simulation modeling technology named synchronous real-time simulation (SRS) is proposed. Instead of running conventional programs on a microprocessor, this new technology adopts several concepts from electronic area, such as using electronic signals to mimic the behavior of entities and using specifically designed circuits to mimic system resources. Besides, a time-scaling simulation method is employed. The method uses an on-board global clock to synchronize all activities performed on different emulators, and by this way tremendous overhead on synchronization can be avoided. Experiments on the prototype simulator demonstrate the validity of the new modeling technology, and also show that tremendous speedup compared to conventional software-based simulation methods can be achieved.