Browsing by Author "Wang, Bixuan"

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    Dynamic RON Free 1.2 kV Vertical GaN JFET
    Yang, Xin; Zhang, Ruizhe; Wang, Bixuan; Song, Qihao; Walker, Andy; Pidaparthi, Subhash; Drowley, Cliff; Zhang, Yuhao (IEEE, 2024)
    Dynamic on-resistance (RON) or threshold voltage (VTH) instability caused by charge trapping is one of the most crucial reliability concerns of some GaN high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic RON and VTH stability of an industrial vertical GaN transistor-NexGen’s 1200V/70mΩ fin-channel JFET, fabricated on 100 mm bulk GaN substrates. A circuit setup is deployed for the in-situ measurement of the dynamic RON under steady-state switching. The longer-term stability of RON and VTH is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no RON or VTH shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices towards power electronics applications.
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    Dynamic Gate Breakdown of p-Gate GaN HEMTs in Inductive Power Switching
    Wang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-02)
    We employ a new circuit method to characterize the gate dynamic breakdown voltage (BVdyn) of Schottky-type p-gate GaN HEMTs in power converters. Different from prior pulse I-V and DC stress tests, this method features a resonance-like gate ringing with the pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. At the increased pulse width, the gate BVdyn shows a decrease and then saturation at 21~22 V. Moreover, the gate BVdyn increases with temperature and is higher under the hard switching than that under the drain-source grounding condition. In the 400 V hard switching at 150 oC, the gate BVdyn reaches 27.5 V. Such impact of the drain switching locus and temperature on the gate BVdyn is not seen in Si and SiC power transistors tested in the same setup. These results are explained by a physics model that accounts for the electrostatics in the p-GaN gate stack in hard switching and at high temperatures. This work unveils new physics critical to the gate robustness of p-gate GaN HEMTs and manifest the necessity of the gate robustness evaluation in inductive switching conditions.
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    Gate Lifetime of P-Gate GaN HEMT in Inductive Power Switching
    Wang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-06)
    The small gate overvoltage margin is a crucial concern in applications of GaN Schottky-type p-gate high electron mobility transistors (SP-HEMTs). The parasitic inductance of the gate loop can induce repetitive gate-voltage (VG) spikes during the device turn-on transients. However, the gate lifetime of the GaN SP-HEMTs under VG overshoot in power converters still remains unclear. We fill this gap by developing a new circuit method to measure the gate switching lifetime. The method features several capabilities: 1) LC-resonance-like VG overshoots with pulse width down to 20 ns and dVG/dt up to 2 V/ns; 2) adjustable power loop condition including the drain-source grounded (DSG) as well as the hard switching (HSW); and 3) repetitive switching test at an adjustable switching frequency (fSW). We use this method to test over 150 devices, and found that the gate lifetimes under a certain peak magnitude of VG overshoot (VG(PK)) can be fitted by both Weibull and Lognormal distributions. The gate lifetime is primarily determined by the number of switching cycles and is higher under the HSW than under the DSG conditions. Finally, the max VG(PK) for 10-year gate lifetime is predicted under different fSW in both DSG and HSW conditions. The results provide direct reference for GaN SP-HEMT’s converter applications and a new method for the device gate qualification.
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    Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method
    Wang, Bixuan; Zhang, Ruizhe; Song, Qihao; Wang, Hengyu; He, Quanbo; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2024-01)
    The small gate overvoltage margin is a key reliability concern of the GaN Schottky-type p-gate high electron mobility transistor (GaN SP-HEMT). Current evaluation of gate reliability in GaN SP-HEMTs relies on either the DC bias stress or pulse I-V method, neither of which resembles the gate voltage (VGS) overshoot waveform in practical converters. This work develops a new circuit method to characterize the gate robustness and reliability in GaN SP-HEMTs, which features a resonance-like VGS ringing with pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. Using this method, the gate's single-pulse failure boundary, i.e., dynamic gate breakdown voltage (BVDYN), is first obtained under the hard switching (HSW) and drain-source grounded (DSG) conditions. The gate's switching lifetime is then tested under the repetitive VGS ringing, and the number of switching cycles to failure (SCTF#) is fitted by Weibull or Lognormal distributions. The SCTF# shows a power law relation with the VGS peak value and little dependence on the switching frequency. More interestingly, the gate's BVDYN and lifetime are both higher in HSW than those in DSG, as well as at higher temperatures. Such findings, as well as the gate degradation behaviors in a prolonged overvoltage stress test, can be explained by the time-dependent Schottky breakdown mechanism. The gate leakage current is found to be the major precursor of gate degradation. At 125 oC and 100 kHz, the VGS limits for a 10-year lifetime are projected to be ∼6 V and ∼10 V under the DSG and HSW conditions, respectively. These results provide a new qualification method and reveal new physical insights for gate reliability and robustness in p-gate GaN HEMTs.