Browsing by Author "Wang, Shen"

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    Design and Analysis of a Low-Power Low-Voltage Quadrature LO Generation Circuit for Wireless Applications
    Wang, Shen (Virginia Tech, 2012-08-31)
    The competitive market of wireless communication devices demands low power and low cost RF solutions. A quadrature local oscillator (LO) is an essential building block for most transceivers. As the CMOS technology scales deeper into the nanometer regime, design of a low-power low-voltage quadrature LO still poses a challenge for RF designers. This dissertation investigates a new quadrature LO topology featuring a transformer-based voltage controlled oscillator (VCO) stacked with a divide-by-two for low-power low-voltage wireless applications. The transformer-based VCO core adopts the Armstrong VCO configuration to mitigate the small voltage headroom and the noise coupling. The LO operating conditions, including the start-up condition, the oscillation frequency, the voltage swing and the current consumption are derived based upon a linearized small-signal model. Both linear time-invariant (LTI) and linear time-variant (LTV) models are utilized to analyze the phase noise of the proposed LO. The results indicate that the quality factor of the primary coil and the mutual inductance between the primary and the secondary coils play an important role in the trade-off between power and noise. The guidelines for determining the parameters of a transformer are developed. The proposed LO was fabricated in 65 nm CMOS technology and its die size is about 0.28 mm2. The measurement results show that the LO can work at 1 V supply voltage, and its operation is robust to process and temperature variations. In high linearity mode, the LO consumes about 2.6 mW of power typically, and the measured phase noise is -140.3 dBc/Hz at 10 MHz offset frequency. The LO frequency is tunable from 1.35 GHz to 1.75 GHz through a combination of a varactor and an 8-bit switched capacitor bank. The proposed LO compares favorably to the existing reported LOs in terms of the figure of merit (FoM). More importantly, high start-up gain, low power consumption and low voltage operation are achieved simultaneously in the proposed topology. However, it also leads to higher design complexity. The contributions of this work can be summarized as 1) proposal of a new quadrature LO topology that is suitable for low-power low-voltage wireless applications, 2) an in-depth circuit analysis as well as design method development, 3) implementation of a fully integrated LO in 65 nm CMOS technology for GPS applications, 4) demonstration of high performance for the design through measurement results. The possible future improvements include the transformer optimization and the method of circuit analysis.
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    Modeling and Design of Planar Integrated Magnetic Components
    Wang, Shen (Virginia Tech, 2003-07-21)
    Recently planar magnetic technologies have been widely used in power electronics, due to good cooling and ease of fabrication. High frequency operation of magnetic components is a key to achieve high power density and miniaturization. However, at high frequencies, skin and proximity effect losses in the planar windings become significant, and parasitics cannot be ignored. This piece of work deals with the modeling and design of planar integrated magnetic component for power electronics applications. First, one-dimensional eddy current analysis in some simple winding strategies is discussed. Two factors are defined in order to quantify the skin and proximity effect contributions as a function of frequency. For complicated structures, 2D and 3D finite element analysis (FEA) is adopted and the accuracy of the simulation results is evaluated against exact analytical solutions. Then, a planar litz structure is presented. Some definitions and guidelines are established, which form the basis to design a planar litz conductor. It can be constructed by dividing the wide planar conductor into multiple lengthwise strands and weaving these strands in much the same manner as one would use to construct a conventional round litz wire. Each strand is subjected to the magnetic field everywhere in the winding window, thereby equalizing the flux linkage. 3D FEA is utilized to investigate the impact of the parameters on the litz performance. The experimental results verify that the planar litz structure can reduce the AC resistance of the planar windings in a specific frequency range. After that, some important issues related to the planar boost inductor design are described, including core selection, winding configuration, losses estimation, and thermal modeling. Two complete design examples targeting at volume optimization and winding parasitic capacitance minimization are provided, respectively. This work demonstrates that planar litz conductors are very promising for high frequency planar magnetic components. The optimization of a planar inductor involves a tradeoff between volumetric efficiency and low value of winding capacitance. Throughout, 2D and 3D FEA was indispensable for thermal & electromagnetic modeling.