Browsing by Author "Zhang, Ruizhe"

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    1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier
    Qin, Yuan; Xiao, Ming; Zhang, Ruizhe; Xie, Qingyun; Palacios, Tomás; Wang, Boyan; Ma, Yunwei; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Srijanto, Bernadeta R.; Zhang, Yuhao (IEEE, 2023-07)
    This work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plane junction electric field of 2.8 MV/cm. The device also shows low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 m ·cm2. Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.
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    Dynamic RON Free 1.2 kV Vertical GaN JFET
    Yang, Xin; Zhang, Ruizhe; Wang, Bixuan; Song, Qihao; Walker, Andy; Pidaparthi, Subhash; Drowley, Cliff; Zhang, Yuhao (IEEE, 2024)
    Dynamic on-resistance (RON) or threshold voltage (VTH) instability caused by charge trapping is one of the most crucial reliability concerns of some GaN high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic RON and VTH stability of an industrial vertical GaN transistor-NexGen’s 1200V/70mΩ fin-channel JFET, fabricated on 100 mm bulk GaN substrates. A circuit setup is deployed for the in-situ measurement of the dynamic RON under steady-state switching. The longer-term stability of RON and VTH is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no RON or VTH shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices towards power electronics applications.
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    Dynamic Gate Breakdown of p-Gate GaN HEMTs in Inductive Power Switching
    Wang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-02)
    We employ a new circuit method to characterize the gate dynamic breakdown voltage (BVdyn) of Schottky-type p-gate GaN HEMTs in power converters. Different from prior pulse I-V and DC stress tests, this method features a resonance-like gate ringing with the pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. At the increased pulse width, the gate BVdyn shows a decrease and then saturation at 21~22 V. Moreover, the gate BVdyn increases with temperature and is higher under the hard switching than that under the drain-source grounding condition. In the 400 V hard switching at 150 oC, the gate BVdyn reaches 27.5 V. Such impact of the drain switching locus and temperature on the gate BVdyn is not seen in Si and SiC power transistors tested in the same setup. These results are explained by a physics model that accounts for the electrostatics in the p-GaN gate stack in hard switching and at high temperatures. This work unveils new physics critical to the gate robustness of p-gate GaN HEMTs and manifest the necessity of the gate robustness evaluation in inductive switching conditions.
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    Gate Lifetime of P-Gate GaN HEMT in Inductive Power Switching
    Wang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-06)
    The small gate overvoltage margin is a crucial concern in applications of GaN Schottky-type p-gate high electron mobility transistors (SP-HEMTs). The parasitic inductance of the gate loop can induce repetitive gate-voltage (VG) spikes during the device turn-on transients. However, the gate lifetime of the GaN SP-HEMTs under VG overshoot in power converters still remains unclear. We fill this gap by developing a new circuit method to measure the gate switching lifetime. The method features several capabilities: 1) LC-resonance-like VG overshoots with pulse width down to 20 ns and dVG/dt up to 2 V/ns; 2) adjustable power loop condition including the drain-source grounded (DSG) as well as the hard switching (HSW); and 3) repetitive switching test at an adjustable switching frequency (fSW). We use this method to test over 150 devices, and found that the gate lifetimes under a certain peak magnitude of VG overshoot (VG(PK)) can be fitted by both Weibull and Lognormal distributions. The gate lifetime is primarily determined by the number of switching cycles and is higher under the HSW than under the DSG conditions. Finally, the max VG(PK) for 10-year gate lifetime is predicted under different fSW in both DSG and HSW conditions. The results provide direct reference for GaN SP-HEMT’s converter applications and a new method for the device gate qualification.
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    Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method
    Wang, Bixuan; Zhang, Ruizhe; Song, Qihao; Wang, Hengyu; He, Quanbo; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2024-01)
    The small gate overvoltage margin is a key reliability concern of the GaN Schottky-type p-gate high electron mobility transistor (GaN SP-HEMT). Current evaluation of gate reliability in GaN SP-HEMTs relies on either the DC bias stress or pulse I-V method, neither of which resembles the gate voltage (VGS) overshoot waveform in practical converters. This work develops a new circuit method to characterize the gate robustness and reliability in GaN SP-HEMTs, which features a resonance-like VGS ringing with pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. Using this method, the gate's single-pulse failure boundary, i.e., dynamic gate breakdown voltage (BVDYN), is first obtained under the hard switching (HSW) and drain-source grounded (DSG) conditions. The gate's switching lifetime is then tested under the repetitive VGS ringing, and the number of switching cycles to failure (SCTF#) is fitted by Weibull or Lognormal distributions. The SCTF# shows a power law relation with the VGS peak value and little dependence on the switching frequency. More interestingly, the gate's BVDYN and lifetime are both higher in HSW than those in DSG, as well as at higher temperatures. Such findings, as well as the gate degradation behaviors in a prolonged overvoltage stress test, can be explained by the time-dependent Schottky breakdown mechanism. The gate leakage current is found to be the major precursor of gate degradation. At 125 oC and 100 kHz, the VGS limits for a 10-year lifetime are projected to be ∼6 V and ∼10 V under the DSG and HSW conditions, respectively. These results provide a new qualification method and reveal new physical insights for gate reliability and robustness in p-gate GaN HEMTs.
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    Power device breakdown mechanism and characterization: review and perspective
    Zhang, Ruizhe; Zhang, Yuhao (IOP Publishing, 2023-04)
    Breakdown voltage (BV) is arguably one of the most critical parameters for power devices. While avalanche breakdown is prevailing in silicon and silicon carbide devices, it is lacking in many wide bandgap (WBG) and ultra-wide bandgap (UWBG) devices, such as the gallium nitride high electron mobility transistor and existing UWBG devices, due to the deployment of junction-less device structures or the inherent material challenges of forming p-n junctions. This paper starts with a survey of avalanche and non-avalanche breakdown mechanisms in WBG and UWBG devices, followed by the distinction between the static and dynamic BV. Various BV characterization methods, including the static and pulse I-V sweep, unclamped and clamped inductive switching, as well as continuous overvoltage switching, are comparatively introduced. The device physics behind the time- and frequency-dependent BV as well as the enabling device structures for avalanche breakdown are also discussed. The paper concludes by identifying research gaps for understanding the breakdown of WBG and UWBG power devices.
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    Robustness of Gallium Nitride Power Devices
    Zhang, Ruizhe (Virginia Tech, 2023-09-05)
    Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids.
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    Superjunction Power Transistors With Interface Charges: A Case Study for GaN
    Ma, Yunwei; Xiao, Ming; Zhang, Ruizhe; Wang, Han; Zhang, Yuhao (2019-12-13)
    Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges for the first time. In our model, two approaches are proposed to compensate interface charges, by the modulation of the SJ doping or the SJ geometry. Based on our model, an analytical study is conducted for GaN SJ transistors, revealing the design windows and optimal values of doping concentration and pillar width as a function of interface charge density. Finally, TCAD simulation is performed for vertical GaN SJ transistors, which validated our analytical model. Our results show that, with optimal designs, interface charges would only induce small degradation in the performance of GaN SJ devices. However, with the increased interface charge density, the design windows for pillar width and doping concentration become increasingly narrow and the upper limit in the pillar width window reduces quickly. When the interface charge density exceeds similar to 3X10(12) cm(-2), the design window of pillar width completely falls into the sub-micron range, indicating significant difficulties in fabrication. Vertical GaN SJ transistors with interface charges retain great advantages over conventional GaN power transistors, but have narrower design windows and require different design rules compared to ideal GaN SJ devices.
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    Third Quadrant Operation of 1.2-10 kV SiC Power MOSFETs
    Zhang, Ruizhe (Virginia Tech, 2022-04-22)
    The third quadrant (3rd-quad) conduction (or reverse conduction) of power transistors is critical for synchronous power converters. For power metal-oxide-semiconductor field-effect-transistors (MOSFETs), there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is well known that, for 1.2 kV silicon carbide (SiC) planar MOSFETs, the conduction loss in the 3rd-quad is reduced by turning on the MOS channel with a positive gate bias (VGS) and keeping the dead time as small as possible. Under this scenario, the current is conducted through both paths, allowing the device to take advantage of the zero 3rd-quad forward voltage drop (VF3rd) of the MOS channel path and the small differential resistance of the body diode path. However, in this thesis work, this popular belief is found to be invalid for power MOSFETs with higher voltage ratings (e.g., 3.3 kV and 10 kV), particularly at high temperatures and current levels. The aforementioned MOS channel and body diode paths compete in the device’s 3rd-quad conduction, and their competition is affected by VGS and device structure. This thesis work presents a comparative study on the 3rd-quad behavior of 1.2 kV to 10 kV SiC planar MOSFET through a combination of device characterization, TCAD simulation and analytical modeling. It is revealed that, once the MOS channel turns on, it changes the potential distribution within the device, which further makes the body diode turn on at a source-to-drain voltage (VSD) much higher than the built-in potential of the pn junction. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on over the entire practical VSD range. As a result, the positive VGS leads to a completely unipolar conduction via the MOS channel, which could induce a higher VF3rd than the bipolar body diode at high temperatures. Circuit test is performed, which validates that a negative VGS control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures in 10 kV SiC planar MOSFET. The study is also extended to the trench MOSFET, another major structure of commercial SiC MOSFETs. Based on the revealed physics for planar MOSFETs, the optimal VGS control for the 3rd-quad conduction in different types of commercial trench MOSFETs is discussed, which provides insights for the design of high-voltage trench MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs.