Now showing items 1-4 of 4
Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs
(Virginia Tech, 2010-11-19)
FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed has resulted in longer runtimes of the implementation tools. We ...
Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity
(Virginia Tech, 2010-08-05)
FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We ...
Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity
(Virginia Tech, 2010-09-01)
FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We address ...
High-Level CSP Model Compiler for FPGAs
(Virginia Tech, 2010-12-14)
The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently raised a need for high-level ...