Now showing items 1-2 of 2
Branch Guided Metrics for Functional and Gate-level Testing
(Virginia Tech, 2015-03-31)
With the increasing complexity of modern day processors and system-on-a-chip (SOCs), designers invest a lot of time and resources into testing and validating these designs. To reduce the time-to-market and cost, the ...
Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution
(Virginia Tech, 2015-03-18)
Considerable research has been directed towards efficient test stimuli generation for Register Transfer Level (RTL) circuits. However, stimuli generation frameworks are still not capable of generating effective stimuli for ...